Problem putting components together :/(vhdl)

Altera_Forum · ‎06-27-2011

hi,

I have to do a project for college that have a transmiter and a receiver, which can only comunicate by a signal(std_logic). So i did it, I made 2 components individually and then I did the temporal simulation, both (transmiter and receiver) worked nice. But now, I've got this problem putting them together. Everything is ok, but the receiver stopped working. its state machine is always at s0(it should go to s1 when the synch sequence is right, and it is!). Well, this is the top of the hierarchy:

library ieee;
use ieee.std_logic_1164.all;
entity top is
	port
		(
		bit1	: out std_logic;
		----------------------------------------------
		CLOCK_50	: in std_logic;
		SW			: in std_logic_vector(8 downto 0);
		KEY0		: in std_logic;
		KEY1		: in std_logic;
		KEY2		: in std_logic;
		HEX0		: out std_logic_vector(6 downto 0);
		HEX1		: out std_logic_vector(6 downto 0);
		HEX2 		: out std_logic_vector(6 downto 0);
		HEX3 		: out std_logic_vector(6 downto 0);
		LEDR0		: out std_logic;
		LEDG0		: out std_logic
		);
end entity;
architecture beh_top of top is
		signal meio			: std_logic;
		signal display		: std_logic_vector(27 downto 0);
--------------------------------top_transmisor-------------------------------------------------------------------
component top_transmissor
port
	(
	CLOCK_1		: in std_logic;
	reset_key	: in std_logic;
	push_key	: in std_logic;
	posicao 	: in std_logic_vector(4 downto 0);--chaves
	saida		: out std_logic --envia para receptor
	);
end component;
--------------------------------top_receptor----------------------------------------------------------------------	
component top_receptor
port
	(
	CLOCK_1		: in std_logic;
	entrada		: in std_logic;	
	key_reset	: in std_logic;
	chaves		: in std_logic_vector(3 downto 0);
	saida		: out std_logic_vector(27 downto 0);
	ledr		: out std_logic;
	ledg		: out std_logic
	);
end component;
begin
--------------------------------------SINAIS <= ENTRADA/SAIDA-----------------------------------------------------
		HEX0(6 downto 0)		<= display(6 downto 0);
		HEX1(6 downto 0)		<= display(13 downto 7);
		HEX2(6 downto 0)		<= display(20 downto 14);
		HEX3(6 downto 0)		<= display(27 downto 21);
		bit1<=meio;
------------------------------------------COMPONENTES
					t0	: top_transmissor port map (CLOCK_50, KEY1, KEY0, SW(4 downto 0), meio);
					r0	: top_receptor port map (CLOCK_50, meio, KEY2, SW(8 downto 5), display, LEDR0, LEDG0);
end beh_top;

The receiver work alone, but not when I put them together...

(I didn't post the transmiter and the receiver components because each one have more than 600 lines)

Thanks to all and sorry by the bad english

Altera_Forum · ‎06-27-2011

Sounds like a specification problem. If there are no compilation errors with the top level, I have no idea why the whole thing is not working.

This is the part we call debugging, and usually takes up most of your time.