Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Problem using set_min_delay between Quartus and Timequest. Results between the two tools are inconsistent.


I'm using a test design to examine why my set_max/min_delay constraints are not working. It appears that Quartus uses the set_min_delay constraint incorrectly during compile.


Setup: The design has a few outputs with varying levels of combinational logic between the clock and the output pins.


Constraints: The clock is attached to the output pin of the global clock driver giving ~1.7 to 1.9ns clock delay over the network. It is related to no other clocks. These are the pertinent constraints:

create_clock -name clk_25 -period 40 -waveform {0 20} [get_pins {U0_pll_50_25_400|pll_50_25_400_inst|altera_pll_i|outclk_wire[0]~CLKENA0|outclk}]

set out_clk clk_25

set_max_delay -from $out_clk -to [get_keepers {OUTA[*]}] 14.000

set_min_delay -from $out_clk -to [get_ports {OUTA[*]}] 5.00


We can ignore the set_max_delay as it appears to work normally.


First off, Timequest appears to work normally. When I vary the minimum constraint (without recompiling) it fails when the clock path + data path > min_delay. All is good.


The problem is that that constraint does not work with Quartus. I recompiled the design with varying min_delay constraints and these are the results I found:


min_delay data_path clock_path

4 7.6-8.2 1.8

4.5 8.4-9.4 1.8

5 9.4-10.2 1.8

5.5 10.3-11.4 1.8

6 11.2-12.2 1.8 (this exceeds max_delay and timing fails)


These results are repeatable. I can get the results I want, but I have to use different constraints between Quartus and Timequest. As an example, if I want 10-12ns delay (clock to IO) I would have to do the following:


Quartus: set_min_delay = 4.5 (mystery math, see above table)

Timequest: set_min_delay = 10 (normal math, 1.8 clk+ 8.2 data)


I'm attaching the project because I'm figure people will assume I've screwed up. If I have, great, let me know where I've gone astray. Otherwise I really need a solution. The FAA doesn't really like the "just because" engineering solution.


Thanks in advance,







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I played with the set_min_delay value on the full project and these were the results. It looks a lot like the min_delay drives the tool to generate a data path ~twice that value (but not quite).


min_delay data path clk path

9 18.7-21.7 2.3

8 16.6-19.4 2.3

7 14.1-16.8 2.3

6 11.4-14.6 2.3

5 9.4-12.4 2.3

4 6.6-9.3 2.3


Thanks in advance.


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For Input/output port, you have to use set_input_delay / set_output_delay. Can you try?

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I didn't see any issue there since the timing result for that signal "OUTA" could meet the min and max requirement set by the constraint. Refer to the screenshot below, Fitter is adding delay at the clock and data path to meet the min value of 5ns.




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posted a file.
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