Problem with Hello-World design

[Altera_Forum]

Hello, 

 Actually, a problem and a few questions:   So I'm pretty new to Quartus and FPGAs in general. I have an older DSP dev kit to play with that uses the Stratix EP1S80B956C6. This device was still available in the new project wizard when setting up a project in Quartus II. I used the schematic editor to put together something very simple; an 8-bit AND gate made up of eight one-bit AND gates, two buses connected to input pins, and one bus connected to output pins. Compilation failed with the following error:   "Error: There is no valid device available"   Searching for this error in the help system returned nothing, and I got nothing searching this forum and Google. It seems wierd because I certainly do have a device, which is the EP1S80B956C6, and Quartus knows this. The online tutorials don't mention having to tell any other component the device name, unless I missed something. Any ideas about what might be going wrong?   I'm also confused about some aspects of the schematic editor. What is the difference between a bus and a conduit? I have a concept of buses from circuit CAD tools like Eagle, and the naming convention seems to be similar (i.e. you must give a bus a name that ends with [N..M], where N and M are integers). However, there are two things I can't figure out about using buses in Quartus:   1.) I'm assuming that connecting a wire to a bus requires the user to give the wire the same name as the bus, but append a single integer to the name instead of [N..M]. Doing this requires a lot of clicking, and it seems like there should be a shortcut for naming wires like this. Is there?   2.) Lots of times I like to make a schematic where a bus segment branches into many wires, and is left unterminated. That way, I have a nice visual reminder of which nodes are bundled into a bus, and that there should be more similar bus segments somewhere else in the schematic. Quartus seems to complain about unterminated bus segments with a little X on the ends. Must I terminate busses in Quartus, or is there a way to get rid of those, or can I just ignore them?   Thanks for any help!

[Altera_Forum]

I believe that a bus is a collection of related wires that form a single data word and can be reference as one name.e.g, data_out. Whereas a conduit is just a way to tidy up a block diagram by bunching wires and buses together. The Quartus help should explain this though.

[Altera_Forum]

--- Quote Start ---    1.) I'm assuming that connecting a wire to a bus requires the user to give the wire the same name as the bus, but append a single integer to the name instead of [N..M]. Doing this requires a lot of clicking, and it seems like there should be a shortcut for naming wires like this. Is there?    --- Quote End ---   From what I know, there is not such a shortcut. Quartus relies more on wire naming than on actual graphical connections, especially when merging buses and wires. Quartus schematic editor is not very smart. I have used better editors in the past. I think this is because Altera focused Quartus for HDL use and the schematic editor is only for connecting main system blocks or for very very simple designs. If you need to make a lot of wiring you'd better use a real CAD.    --- Quote Start ---   2.) Lots of times I like to make a schematic where a bus segment branches into many wires, and is left unterminated. That way, I have a nice visual reminder of which nodes are bundled into a bus, and that there should be more similar bus segments somewhere else in the schematic. Quartus seems to complain about unterminated bus segments with a little X on the ends. Must I terminate busses in Quartus, or is there a way to get rid of those, or can I just ignore them?    --- Quote End ---   Don't mind the little X on the ends of segments. They are always there if the wire/bus is not graphically connected to anything, even if those signals are actually connected somewhere else in the schematic. Quartus doesn't complain about anything when you draw the wires; however, in the processing phase, it will complain if the unterminated input wires are actually undriven signals.  Regards