Problem with PowerPlay Power Analyser

[Altera_Forum]

Hi, 

I am new to FPGA world. I want to measure power by Quartus PowerPlay of an 8 bit counter. I simulated it with a test bench in ModelSim and generated VCD file. (Attached: counter.vhd)   I used the following commands to get VCD from ModelSim Altera:   vsim> vcd file vcdtest.vcd vsim> vcd add -r /*  vsim> run 2us vsim> vcd checkpoint vsim> quit -sim     Then in Quartus, i chose Cyclone II FPGA device.  I assinged the generaed VCD file to get the toggle rates.  Also, enabled glitch filtering. But, I am getting "Low" confidence level for power estimation in the report.   I tried several designs to estimate power in the above methed. But, the power consumption is always around 110mw and the confidence level is "LOW".    please let me know where I am doing wrong? please help...

[Altera_Forum]

I think the net-list that you are using to generate the VCD file is that or RTL level and not gate-level. 

 Try to generate a gate level net list (.vo) file for your counter use it instead of your .v file in the simulation then generate the vcd file and I think it would increase the confidence level.

[Altera_Forum]

Thanks. You are right.  

 I generated gate level code (.VHO) from VHDL code using Quartus. Quartus also generated a .do script to compile the code in ModelSim. Then I simulated the gate level code with RTL stimulator in ModelSim and generated VCD file. The power confidence level was High.   Below are the steps that I used to calculate power, hope it will be useful for beginners.   ----------- DUT = design for which we want to measure power STM = stimulation vectors TOP = wrapper for DUT and STM   1. write DUT, STM, TOP. simulate using ModelSim. See wave form to verify   2. In Quartus, Make project with only DUT file, compile   3. In Quartus, Assignment->Settings-> EDA Tool -> Simulation Tool name: ModelSim Altera [check] Run gate level --will creat gate level .vho file (we need to make VCD from gate level DUT) --also will creat a .do file of how to compile it in ModelSim language: vhdl [chk] map, [chk] glitch   OK 2. Compile design, Modelsim will open autometically, quit   3. Lunch ModelSim set directory File->load--> .do file (to compile .vho file of DUT) remove "FOR ALL" statements from TOP file compile stm, top Simulate->start simulation select TOP in VSIM prompt: vsim> vcd file my_vcd.vcd vsim> vcd add -r /* vsim> run 2000ns vsim> vcd checkpoint vsim> quit -sim   4. In Quartus --> Assignments-->Settings-->powerplay--> assign VCD file [entity DUT] [chk] write saf [chk] write block [chk] glitch 5. processign ->start--> powerplay 6. Tools--advisor-->powerplay (for more optimization)

[Altera_Forum]

Hey Tareq, 

 I'm new to Quartus II as well, but I have found an easier way to run gate level simulation with ModelSim. Basically the idea is to use leverage NativeLink built-in Quartus II that supports running testbench with the bundled ModelSim Altera Edition.  NativeLink allows you to launch top level simulation in ModelSim Altera without having to type anything in ModelSim console. This saves a bit of time and also streamlines the flow. NativeLink settings can be found in Assignments > Settings > EDA Tool Settings > Simulation. Make sure you select ModelSim-Altera as your simulation tool under Assignments > Settings > EDA Tool Settings.   The flow is as follows:  (1) Write your design files in HDL of your choice (verilog/VHDL). Then write your testbench, save the testbench in the same folder, and you don't necessary have to add it to the project.   (2) Go to Assignments > Settings > EDA Tool Settings > Simulation, click on "Compile test bench radio button in NativeLink Settings". Click on Test Benches button to add your testbench code. Make sure you check Generate Value Change Dump file script and make sure your design instance name matches the one you entered in Test Bench Settings.   (3) Compile your design   (4) Tool > Run EDA Simulation Tool > EDA Gate Level Simulation   (5) In ModelSim-Altera console, type <design_name>_dump_all_vcd_nodes.tcl, and hit enter. This will generate the VCD file you need for powerplay power estimation. You can also just type <design_name> and scroll down from the selection menu, _dump_all_vcd_nodes.tcl should be one of the options.  Hope this helps. So far this flow has saved me some headache from figuring out how to run ModelSim-Altera from ground up.

[Altera_Forum]

Hello guys..I'm also doing power analysis in quartus and whateve i do I always got low estimation confidence..I just want to clear what are these terms Sir tareq_992403 posted. 

 STM = stimulation vectors TOP = wrapper for DUT and STM  and how to create this in modelsim..  please help me guys..Thankyou