I have a design that can be used for an Arria2 or for a Xilinx FPGA.
On schematics I have a generic that choose what to generate but I'm having a little big problem.
The head of the file, generated by HDL Designer, do something like:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.all;
USE UNISIM.VPKG.all;
LIBRARY altera_mf;
USE altera_mf.all;
LIBRARY Lib_Fifo_Altera;
LIBRARY Lib_Geral;The bold lines just give me the following error:
Error (10481): VHDL Use Clause error at fifo_16x69_fwft_ws_gen_sc_struct.vhd(55): design library "UNISIM" does not contain primary unit "VCOMPONENTS"I have something like 50 structs and it's a mess hand editing one be one, just to comment that lines and have to do it again if I generate the struct. :cry:
How can I put Quartus ignoring that Lib's?
Thanks for the help
