Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17259 Discussions

Problem with assigning clock

Altera_Forum
Honored Contributor II
3,103 Views

Hello, 

I am using a Quartus II 14.0 software and SoCkit rev.C (with 5CSXFC6D6F31C8NES in it). I have a problem with assigning clock in my project. I want to make a simple project which will use slide buttons (as inputs), LEDs (outputs) and clock. First two of them are assigned properly (I have compliled a project without clock input and it was fine) but I have a huge problem in using clock. I want to use only one clock (treated as global) but I think I have an error in qsf file. 

 

--- Quote Start ---  

# --------------------------------------------------------------------------# ## Copyright (C) 1991-2014 Altera Corporation. All rights reserved.# Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, the Altera Quartus II License Agreement,# the Altera MegaCore Function License Agreement, or other # applicable license agreement, including, without limitation, # that your use is for the sole purpose of programming logic # devices manufactured by Altera and sold by Altera or its # authorized distributors. Please refer to the applicable # agreement for further details.# # --------------------------------------------------------------------------# # # Quartus II 64-Bit# Version 14.0.0 Build 200 06/17/2014 SJ Full Version# Date created = 09:04:15 August 05, 2014# # --------------------------------------------------------------------------# # # Notes:# # 1) The default values for assignments are stored in the file:# tutorial_assignment_defaults.qdf# If this file doesn't exist, see file:# assignment_defaults.qdf# # 2) Altera recommends that you do not modify this file. This# file is updated automatically by the Quartus II software# and any changes you make may be lost or overwritten.# # --------------------------------------------------------------------------#  

 

 

 

 

set_global_assignment -name FAMILY "Cyclone V" 

set_global_assignment -name DEVICE 5CSXFC6D6F31C8 

set_global_assignment -name TOP_LEVEL_ENTITY tutorial 

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0 

set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:15 AUGUST 05, 2014" 

set_global_assignment -name LAST_QUARTUS_VERSION 14.0 

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 

set_global_assignment -name VHDL_FILE tutorial.vhd 

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" 

set_location_assignment PIN_AF10 -to f 

set_location_assignment PIN_V25 -to x1 

set_location_assignment PIN_W25 -to x2 

set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf 

set_global_assignment -name CDF_FILE simulation/Chain1.cdf 

set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF 

set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF 

set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4" 

set_global_assignment -name USE_CONFIGURATION_DEVICE ON 

set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON 

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise 

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall 

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise 

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall 

set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ 

set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to f 

set_instance_assignment -name SLEW_RATE 1 -to f 

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk 

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 

--- Quote End ---  

 

I have tried to fix it - I changed assignment from global signal to location, both of them (in this option there were no warning in compilation process such as incomplete assignment) but it didn't help. I have searched a few similar topics in forum but I haven't find answer. I also study an chapter from Quartus handbook but there are no instant formulas how to assign global clock (in qsf file) 

I think it's a basic error but I cannot find it/them.  

Sorry for my bad English. 

Thanks for your response. 

Michal
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
1,963 Views

Does the project, with clock, compile without any constraints? Based on your description I'm not sure you need the 'GLOBAL_SIGNAL' assignment for the clock. 

 

Quartus will identify the clock from your code/schematic. Assuming it goes in on a global clock pin (given your hardware I suspect it does) then all you should need to do is assign the correct pin and I/O standard. Quartus should then assign the clock to a global resource. 

 

Try compiling your design, with the clock, without any clock constraints. This is a useful check that there are no other issues that might be responsible for any compilation errors you're seeing. Once you are happy the source is good you can add the necessary location assignments to the clock. 

 

Cheers, 

Alex
0 Kudos
Altera_Forum
Honored Contributor II
1,963 Views

Project was compiled with 1 constraints when I use only assigment clk as location or as global signal. When I had changed assigsment to both of them there were no errors connected to bad assignments. Constraint was about one not exacly assigned pin.  

So as I understand you I have to assign only as location with correct name of pin and quartus will know that this signal is clock. Am I right? 

If so I have no ideae how to correct project. I tried this before but without good results. I will check again if my assignment to pin as location was proper. 

Thank you for reply.  

Cheers, 

Michal
0 Kudos
Altera_Forum
Honored Contributor II
1,963 Views

Quartus will work out what signals are clocks - yes (and it won't matter what you call them). 

 

So, yes - you simply need to assign the right pin with the right signal name (from your source code) and Quartus will do the rest. 

 

You can fix your project in one of two ways: a) remove all the unwanted assignments from the .qsf (edit the text in the file) or you can do this as intended from within Quartus; or b) (if option a doesn't work for you) create the project again, compile it and add the assignments you need. 

 

Cheers, 

Alex
0 Kudos
Reply