Problem with multiple entities reading from one input

[Altera_Forum]

Hey guys, 

 Doing a school project on the DE2 board (so, minimal code posted if possible), and have some questions about how the board may process some things. We're making a game that looks akin to this: http://imgur.com/nykmsic  Brief description, to give you a feel:  1. Purple wire are control signals and/or feedback signals to the control unit, which governs our state machine. The control unit in turn assigns signals to the appropriate units as indicated.  2. clk is the 50MHz onboard system clock  3. We read input from the user. If the input is "valid," (meaning the user stayed within the board, pressed the right keys for a move, etc etc), it's passed along to the "new board" entity via the orange "move" signal to see if the move is valid. The move is checked according to the algorithm that governs the game, which is complicated, but in the end, the entity outputs a std_logic bit to indicate the validity of the move. If the move is valid, the "new board" on the red wire becomes the blue "board" signal on the next clock cycle. This transition is governed by the "board director" unit. We did this in lieu of using a bus, for reasons of simplicity.   4. The board itself is a user-defined type, consisting to 25 spaces, where each space contains a 6 bit logic vector (actually a record with three separate logic vectors, but no need to split hairs) describing the state of the space (if there's a piece on it, who owns the piece, and some other things).   Here's the problem we're having. The board is a signal at the uppermost level, being used by both input and graphics simultaneously. It is only being read, not written to, by these units (board director is the only one that can write to board). But when we compile and program the board, we either get the input working, or the graphics working, but never both. We suspect this might have to do with the board signal itself, but aren't sure.  Basically, I'm asking for help on how we might be able to troubleshoot this issue, if at all. We can't even start troubleshooting the new board entity and its sub-entities until we get them to work together. What should we check?

[Altera_Forum]

lets have a look at some code, and we'll see whats wrong.

[Altera_Forum]

I can confirm that this kind of hierarchical data pathes works generally well in VHDL. 

 There are some special requirements if it uses bidirectional inout ports, similar to a real hardware bus, e.g. all connected components must tristate the port and there can be only one driver for a specific data bit unless you are defining resolved signal types.  A simple way to debug design faults is to disconnect and reconnect the components incrementally and watch when the problem appears.