Problems inferring memory for Arria V

[Altera_Forum]

Hello 

 With my transition from Startix III to Arria V, i thought it to be a good idea to have my block memory inferred instead of instantiated/MegaWizzard generated for better portability. My idea is to just replace whats there, which works perfect for the easier cases. However, I have not found any solution for the following issues:  A: True dual port read enable signals. How can this be realized. Up to now I tried many variants, always ending up with "inferring not possible due to asynchronous output logic". Read-during-write is not a need for me, as this is not occuring by design. In a first step, a single clock is viable. Is there any way to get this running (obviously the HW is there, as the MegaWizzard can do it)?  B: Initialisation of RAM content. I see a correct internal .mif file beeing generated, when I assign hard coded values to the RAM array initialisation (e.g. Info (286033): Parameter INIT_FILE set to db/....mif). However, when assigning data read from a file in the init part of my VHDL code, no initialisation .mif is generated (the assignment itself succeeded well, Modelsim simulation yields perfect results). Does Quartus not support the textio library? How can I get this to run (I dont want to use the synthesis attribute ram_init_file, as simulation does not get that)?  Thanks for any hint!

[Altera_Forum]

VHDL fileio isnt' supported in Quartus, Verilog $readmemb and $readmemh works. 

 For true dual port memory port inference, you can follow the Quartus language templates, accessible in the editor context menu.

[Altera_Forum]

To bad file/textio doesn't work, maybe it will some day?  

In meantime I created a workaround using textio for the simulation in parallel with a ram_init_file attribute pointing to exactly the same .hex file. Not my favorite solution, as my parser may do things differently than the Quartus II one. Anyway, this will do for now.  Concerning the templates: I had a short look into the editor templates and they look to me exactly the same as the ones noted in AN qts_qii51007. None of them has an output enable as far as I can see (searching for the megaWizzard Inputs rden_a/b). I read that others had similar issues, too, but in conjunction with read-during-write the new values and two clocks. That's why I wonder whether rden_a/b can be added to an inferred memory somehow to match/replace the former megaWizzard generated instance.