Processes sensitivity list question

[Altera_Forum]

Hello, 

 OK, simple question if I may from me again in my quest to get things straight in my tiny mind: Looking at this snippet of code VHDL..  SIGNAL slv_Clock : STD_LOGIC; SIGNAL slv_Signal : STD_LOGIC; proc_DoSomething : PROCESS(slv_Clock, slv_Signal) BEGIN IF RISING_EDGE(slv_Clock) THEN IF slv_Signal = '0' THEN --Do something cool END IF; END IF; END PROCESS proc_DoSomething;   Question: What would the point of putting the signal slv_signal in the PROCESS sensitivity list be for?  Thanks again!  Andy

[Altera_Forum]

--- Quote Start ---  Hello,  OK, simple question if I may from me again in my quest to get things straight in my tiny mind: Looking at this snippet of code VHDL..  SIGNAL slv_Clock : STD_LOGIC; SIGNAL slv_Signal : STD_LOGIC; proc_DoSomething : PROCESS(slv_Clock, slv_Signal) BEGIN IF RISING_EDGE(slv_Clock) THEN IF slv_Signal = '0' THEN --Do something cool END IF; END IF; END PROCESS proc_DoSomething;   Question: What would the point of putting the signal slv_signal in the PROCESS sensitivity list be for?  Thanks again!  Andy  --- Quote End ---    No need. process is activated by clk only. If slv was outside clk(before if rising... then yes you need it

[Altera_Forum]

and if you use wait until instead of if rising... then no need for clk either. 

It is all syntax isues which have not been automated but passed to the bewildered programmer and may change tomorrow?

[Altera_Forum]

OK, thanks for answer. I have indeed understood it correctly then (your answer supports what I already knew of this). 

 Reason for asking: In some people's VHDL I see this - a signal that only changes upon a clock edge but appears in the sensitivity list so I was wondering why this may be the case... Guess they needn't have!  wait until...? That's a testbench thing no?  Anyway, thank again!  Andy

[Altera_Forum]

--- Quote Start ---  OK, thanks for answer. I have indeed understood it correctly then (your answer supports what I already knew of this).  Reason for asking: In some people's VHDL I see this - a signal that only changes upon a clock edge but appears in the sensitivity list so I was wondering why this may be the case... Guess they needn't have!  wait until...? That's a testbench thing no?  Anyway, thank again!  Andy  --- Quote End ---    wait unti clk = '1'; is same as if rising_edge(clk) then and leads to registered assignments. This is not wait for 1 ns; ...etc very popular with beginners and Unis

[Altera_Forum]

Gotcha. These sensitivity lists are weird - I am starting to think of them as a simulation tool really to help spot bugs. I have written something that simulates 100% spot on. When I synthesize it, bosh, not as expected. 

 Inane questions that I am asking is me trying to understand the basic basics and as a result trying to determine / understand what the hell is going on in my VHDL!  Still not got there though with my problemette, but good answers on this excellent forum are helping me no end!  Thanks again!  Andy

[Altera_Forum]

Googling 'VHDL sensitivity list' and reading I see comments like this: 

   --- Quote Start ---  Also, the synthesis tools (talking about the Xilinx XST in this case) don't necessarily always respect the process sensitivity list. If you fail to list all the processes whose values are evaluated in the body of the process, the XST will emit a warning saying that it's going to assume that the signals whose values are evaluated are on the sensitivity list. That may lead to differences between behavioral simulations and actual hardware. Keep it in mind.  --- Quote End ---   Hmmm, guess what I'm experiencing!    --- Quote Start ---  ...also, be warned, the sensitivity list has no influence over the behaviour of your design once it is synthesized. It is only used during simulation. Hence it's quite easy to introduce a difference in behaviour between RTL and synthesized code by changes to the sensitivity list. (Note: Depending on the synthesis tool, the sensitivity list may be ignored, or a latch may be inferred  --- Quote End ---   Yep! Been there, seen that.    --- Quote Start ---  All of this can be confusing in the case of using VHDL for synthesis because only a subset of the circuits you describe in VHDL can actually be implemented within a FPGA. For example, you can't have a primitive memory element that is sensitive to two independent clock edges, even though you could describe such a circuit by including two clocks in a sensitivity list.  --- Quote End ---   Guess you really, REALLY have to understand the fundamentals!  Andy

[Altera_Forum]

Understanding the fundamentals is key to writing VHDL. HDL stands for hardware description language - dont understand the hardware, how do you expect to describe it? 

 Most people learn VHDL after learning digital electronics first. Doing this would make most of your misunderstanding problems go away.  Have a read of the coding templates, that outline templates you should follow to infer FPGA base units (registers, rams, etc) in the quartus handbook: http://www.altera.co.uk/literature/hb/qts/qts_qii51007.pdf

[Altera_Forum]

Indeed! I understand the hardware now my task is to get to grips with how to describe it using VHDL. In understanding the nuances and foibles of this decriptive language, with respect to the environment I am using will help me to prevent errors which would otherwise set me off going around in circles. 

 Andy

[Altera_Forum]

--- Quote Start ---  Googling 'VHDL sensitivity list' and reading I see comments like this:   --- Quote Start ---  Also, the synthesis tools (talking about the Xilinx XST in this case) don't necessarily always respect the process sensitivity list. If you fail to list all the processes whose values are evaluated in the body of the process, the XST will emit a warning saying that it's going to assume that the signals whose values are evaluated are on the sensitivity list. That may lead to differences between behavioral simulations and actual hardware. Keep it in mind.  --- Quote End ---    Hmmm, guess what I'm experiencing!  --- Quote End ---    It's even worse with Altera Quartus II: It will output this message:   --- Quote Start ---  Warning (10492): VHDL Process Statement warning at filename.vhd(123): signal "my_signal" is read inside the Process Statement but isn't in the Process Statement's sensitivity list  --- Quote End ---    From this warning perspective I read it like: Hey, you forgot something, don't you want to add it?  But what it really want's to tell me is: Hey, I changed your code (and so your hardware behavior)! But I don't tell you, you have to find it out yourself by measuring that your hardware doesn't do what you told the compiler to synthesize.  That's contradictory to what you find in educational books about VHDL, e.g. Free Range VHDL:   --- Quote Start ---  For the behavioral architecture description, any time there is a change in signals in the process sensitivity list, all of the sequential statements in the process are re-evaluated.  --- Quote End ---    In my opinion: Process Sensitivity lists are useless if the compiler doesn't respect what you write there (= the only signals you want the process to be sensitive to). So don't make effort to fill them out, just use the "all" and the compiler will find out itself which signals he thinks the process is sensitive to - and write your process in a way so that it isn't sensitive to signals you don't want the process to be sensitive to, e.g. make sure the signal change you want to respond to really changed.

[ArushSinha]

It's obviously been a long time and this has been answered but another way is that if you were to do some asynchronous circuit with slave clk and slave signal, you could include in sensitivitylist. Although I can't imagine application for that now.