Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16606 Discussions

Program the Altera MAX-V CPLD using JTAG

Altera_Forum
Honored Contributor II
‎10-23-2017 09:03 PM
1,073 Views

I have previously only been working with Xilinx FPGAs, so I need some help to flash to Altera MAX-V which for me seems to be a bit different from the Xilinx flash procedure. The goal is to flash the MAX-V CPLD using JTAG interface. 

So far I have created and synthesized the design and assigned pins using the Pin Planner application. I have not assigned any JTAG pins manually in the Pin Planner, but I assume pins 14-17 are already assigned for TMS, TDI, TCK, and TDO respectively as default. I wonder if I need to use some kind of IP core in order to use the JTAG interface to flash?
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎10-24-2017 11:30 PM
275 Views

Are you using a development kit or your own board? With a dev kit, there should be a JTAG (10 pin, 2 rows of 5) or USB blaster connection. It does not require pin assignments in the Pin Planner since they are hard pins. If you're using your own board, you must have a 10-pin connection to bring the JTAG connection out for USB Blaster.

0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.