Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Program the Altera MAX-V CPLD using JTAG

Altera_Forum
Honored Contributor II
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I have previously only been working with Xilinx FPGAs, so I need some help to flash to Altera MAX-V which for me seems to be a bit different from the Xilinx flash procedure. The goal is to flash the MAX-V CPLD using JTAG interface. 

So far I have created and synthesized the design and assigned pins using the Pin Planner application. I have not assigned any JTAG pins manually in the Pin Planner, but I assume pins 14-17 are already assigned for TMS, TDI, TCK, and TDO respectively as default. I wonder if I need to use some kind of IP core in order to use the JTAG interface to flash?
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Altera_Forum
Honored Contributor II
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Are you using a development kit or your own board? With a dev kit, there should be a JTAG (10 pin, 2 rows of 5) or USB blaster connection. It does not require pin assignments in the Pin Planner since they are hard pins. If you're using your own board, you must have a 10-pin connection to bring the JTAG connection out for USB Blaster.

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