Project organisation, multiple images on one hardware

[Altera_Forum]

Hi all! 

 I would like to have your options, suggests and comments on how to organise my FPGA project.  The project consists of one hardware, which shall be used with different FPGA images to serve different purposes. The main part of the project contains all the IO stuff, PHYs for hardware components and general components, to be available in all images. A specific functionality is then given by different extra modules connecting the various PHYs. The question is now, how I can organise that reasonably in Quartus. Currently I have all extra modules in the (main) code and just comment/uncomment the connections between them. Unfortunately I also need to comment/uncomment different sections in the .sdc file to get proper timing analysis.  An other thing I'd like to have, is some user-readable version information about the image. So how may I have different text strings and version numbers in each image? Programming in C I would generate different build configurations and use compiler defines to set different strings/parameters and include/exclude files....  Pauliman

[Altera_Forum]

--- Quote Start ---   Currently I have all extra modules in the (main) code and just comment/uncomment the connections between them. Unfortunately I also need to comment/uncomment different sections in the .sdc file to get proper timing analysis.   --- Quote End ---  Why don't you use parameters (Verilog) or generics (VHDL)?  Tcl scripts can be used for synthesis and simulation. Those scripts can set the values of the generics/parameters. The .sdc file is just Tcl, so it can also use the generics/parameters (or different files can be included based on the generics/parameters).    --- Quote Start ---   An other thing I'd like to have, is some user-readable version information about the image. So how may I have different text strings and version numbers in each image?   --- Quote End ---  I use;  * Board identification  * FPGA identification (for multiple FPGAs on a board)  * Design ID  * Build timestamp (passed in as a Tcl generic)  These are all 32-bit registers. Tcl can then format the IDs into strings - no need for the strings to be stored in hardware.  You can also add read-only registers for all the generics/parameters. That way your software can read the design ID, then the generics, and then provide the appropriate hardware-specific functions.  Cheers, Dave

[Altera_Forum]

Hi Dave! 

Thanks for the generic hint. (I'm using vhdl). That sounds exactly what I've been looking for. Can you provide me any sample or suggested reading on how to set that up? How can I driver the synthesis with different configurations and name the images afterwords meaningful? Can I directly us the generic parameter in if() statements in the timequest configuration file?  Once I'm able to driver the synthesis from some kind of tcl-script it shall be quite easy to put some revision information into the image. What I'd also like to have in the image are human readable strings to be accessible as read-only storage on the computer interface. Is there any easier way to do that besides creating .mif files?  Thank You! Pauliman

[Altera_Forum]

--- Quote Start ---   Can you provide me any sample or suggested reading on how to set that up?   --- Quote End ---     Sure. What evaluation boards do you have? If I have the same board, I'll modify an existing example for you.    --- Quote Start ---   How can I driver the synthesis with different configurations and name the images afterwords meaningful?   --- Quote End ---     Its got nothing to do with synthesis, you just copy the file to a new name :) Tcl commands can be used.    --- Quote Start ---   Can I directly us the generic parameter in if() statements in the timequest configuration file?   --- Quote End ---    Sure. In some of my SDC files, I first look to see if a net exists, and then assign a constraint. This allows me to enable/disable features without having to edit the .sdc file.    --- Quote Start ---   What I'd also like to have in the image are human readable strings to be accessible as read-only storage on the computer interface. Is there any easier way to do that besides creating .mif files?   --- Quote End ---    Why bother with strings in the image? You'll be using logic cells unnecessarily. If you are reading the registers directly, reading a vendor ID, product ID, and revision as hex values is adequate. This has served every USB device and PCI device out there quite well :) Ok, USB devices do have strings too.  If you want to store strings in RAM, then you have to use .mif files or Intel Hex files. I prefer the latter.  Cheers, Dave