Python and VHDL

[Altera_Forum]

Hi every body 

 I have a component in VHDL and I wanna making several copy of it and creating a Mesh M*N dimensions with them, if I will define whole the signals between them its take a long times in VHDL because I have to define more than 2000 signals between them and I think its not proper method but I think so I can using the Python to taking instance of them and finally export again to VHDL file. it is mean I using the Python only to definition and communication different signals between several component deposit this component before wrote by VHDL. if it is possible please tell me how can i using the python for do that.

[Altera_Forum]

--- Quote Start ---   I have a component in VHDL and I wanna making several copy of it and creating a Mesh M*N dimensions with them, if I will define whole the signals between them its take a long times in VHDL because I have to define more than 2000 signals between them and I think its not proper method but I think so I can using the Python to taking instance of them and finally export again to VHDL file. it is mean I using the Python only to definition and communication different signals between several component deposit this component before wrote by VHDL. if it is possible please tell me how can i using the python for do that.  --- Quote End ---    You do not need to use Python. You can use VHDL and a generate loop. If the signal indexing is complicated, then you can also use a VHDL function.  Look at the pipelined mux figure and code posted in this thread:  http://www.alteraforum.com/forum/showthread.php?t=41601  and you'll see examples of how to use generate statements.  You can also look at the code for this LFSR/PRBS tutorial  http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip  and in lfsr_tutorial_src\prbs\src\prbs.vhd you'll see how functions can be used to make complicated VHDL easier to read.  Cheers, Dave

[Altera_Forum]

Yes it is true I can generated it by function or for generate loop in VHDL, but I wanna learned how can I using of the Python script language in VHDL files. and this communication between the VHDL files and Python how is it?

[Altera_Forum]

--- Quote Start ---  Yes it is true I can generated it by function or for generate loop in VHDL, but I wanna learned how can I using of the Python script language in VHDL files. and this communication between the VHDL files and Python how is it?  --- Quote End ---    There is no communication.  If you want to use Python to create VHDL, then you would simply use Python to create VHDL files.  If you want to have the Python create the files based on VHDL generics provided in the Quartus GUI, then you will have to use a Tcl pre-flow script to run the Python code.  My advice is that if VHDL can generate the logic you need, then use VHDL. You are overly complicating things if you need to use Python in your scripting flow. If you have to use scripts, then stick with Tcl, and your scripts will then be portable to other users. No-one on this forum will be interested in helping you debug your Python, but you will get help debugging VHDL and Tcl.  Cheers, Dave

[Altera_Forum]

Well, I for one am interested in Python and, specifically, MyHDL as it applies to this use case. I would certainly provide help along these lines... 

 Certainly, coding in Python (or other HLS option) is more interesting than sticking with the staid and rather boring...not to mention _ancient_ (nearly 30 years old!) design paradigm that is coding in Verilog/VHDL/SystemVerilog. :-)  Cheers!  slacker

[Altera_Forum]

You do that if you want.  

Good luck getting it to work with anything other than MyHDL. Also, it is of not use in the job market.

[Altera_Forum]

MyHDL just produces VHDL or Verilog. 

In my experience, all tools that auto-generate HDL for you tend to be rubbish.   PS. System Verilog was only standardised in 2005.

[Altera_Forum]

Hi Slacker, 

  --- Quote Start ---  Well, I for one am interested in Python and, specifically, MyHDL as it applies to this use case. I would certainly provide help along these lines...  Certainly, coding in Python (or other HLS option) is more interesting than sticking with the staid and rather boring...not to mention _ancient_ (nearly 30 years old!) design paradigm that is coding in Verilog/VHDL/SystemVerilog. :-)   --- Quote End ---   The practical reality of designing with FPGAs is that you are "stuck" with using whatever language that the vendor supports. I first selected VHDL because MAX+PLUS II did not support various Verilog constructs. I'm not an expert SystemVerilog user, but it appears to have lots of modern object-oriented constructs ... alas, I see various threads on things that work in Modelsim, but do not work in Quartus.  By all means play with MyHDL, and run the designs through Quartus, there are lots of happy users of the tools. However, once you have spent the time learning an HDL language (ancient though they may be), you'll find that there's really no advantage in using MyHDL over performing similar language tricks in an HDL language.  Cheers, Dave

[Altera_Forum]

Would be nice if those pontificating had actually tried said language/tool...fair enough? 

 MyHDL produces VHDL and Verilog that is quite usable/legible. Sure, it's not supported by a big name company (not sure that offers much value anyway), but the person developing it is by no means a noob to HDL/RTL or the industry as a whole.  It offers automated testbench generation in the end-simulator of your choice (including ModelSim) and works well with all of the freely available simulation tools (iVerilog, GHDL, GTKWave, etc.). Plus, it has the additional benefit of Python's great unit testing options.  Python's also becoming more and more the lingua franca in all sorts of fields.  To each his own, of course, but categorically shutting doors on things like this cannot possibly be good policy if progress and improvement are the end goal. Besides which, 30+ years of what is essentially the same design paradigm is not exactly what I would call progress. Yes, I think I can safely state that the IC design industry (interestingly, FPGA design still follows this paradigm as well...) has succeeded in spite of not because of the "advanced tools" that have been delivered by the EDA industry.  I don't want to start a flame war, but I think ideas should succeed and tools should be used on their own merit, not pre-conceived notions.  Cheers!  slacker

[Altera_Forum]

Hi Slacker, 

   --- Quote Start ---  Would be nice if those pontificating had actually tried said language/tool...fair enough?   --- Quote End ---    It was not my intention to pontificate, I was merely explaining the situation of many of the users of these tools, i.e., we have selected the development languages of VHDL, Verilog, and Tcl, not by choice, but by default.  I did look at MyHDL in its earlier days, and did chat with some of the active developers at the Embedded Systems Conference in San Jose last year. Its a cool looking project and language.  However, since I am already familiar with VHDL and writing testbenches in VHDL, I have not found any incentive to change over to MyHDL (which you can read as "old and set in his ways" if you like).  Feel free to enlighten the curmudgeons amongst this group and write a tutorial showing how to create a reasonably complex system using MyHDL (eg., one that includes MegaCore IP), or fire some ideas back and forth about how people can get started using MyHDL. Perhaps start a new thread called "MyHDL" or "Introduction to MyHDL".  Cheers, Dave

[Altera_Forum]

--- Quote Start ---   To each his own, of course, but categorically shutting doors on things like this cannot possibly be good policy if progress and improvement are the end goal. Besides which, 30+ years of what is essentially the same design paradigm is not exactly what I would call progress. Yes, I think I can safely state that the IC design industry (interestingly, FPGA design still follows this paradigm as well...) has succeeded in spite of not because of the "advanced tools" that have been delivered by the EDA industry.  I don't want to start a flame war, but I think ideas should succeed and tools should be used on their own merit, not pre-conceived notions.  Cheers!  slacker  --- Quote End ---    The design endgame is not VHDL/verilog. Its gates and registers. HDLs are just a well established method to produce and suitably verify these. It has 30 years of momentum, and changing something like this is not easy. MyHDL may be an amazing tool, but without adoption, it will be useless to anyone with it on their CV, and if you're someone with extensive MyHDL experience up against someone who spent the same time in the "advance tools" of the EDA idustry, you're probably not getting that job.  I am a VHDL engineer, but I will admit if you want a job you really need to know SystemVerilog and UVM. Thats what makes you most employable. Companies generally dont invest in tools without a solid background, and those tools need to show some kind of performance or productivity improvement before major companies will even think about trying them out.  Although you would probably argue they are not the same, I have experience using Matlab HDL coder and HDL coder. The former likes to be sold as the "one stop solution" for algorithm -> FPGA development, they like to gloss over the part that its not quite that simple if you want a space and timing optimised solution. Plus its another tool you have to learn to use. HDL coder wraps itself around VHDL/Verilog, but it wants to do everything its way (again, another tool to use etc etc)  Remember, most engineers are not fluent in Python. So thats your first barrier. Its a second language they need to understand (as they will really need to understand the generated Verilog/VHDL). And that is another risk - any language that generates another language will always have some bugs somewhere! (why do people that design PCBs still insist on checking the entire generated netlist, and get it reviewed?)

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

Here's what I think is an interesting question; lets say you are a knowledgeable VHDL or Verilog engineer, and you've decided you really need to get a better handle on test and verification. As I see it you have several options; 

 1. VHDL; Use Jim Lewis' Open Source VHDL Verification Methodology (OS-VVM)  http://osvvm.org/  2. SystemVerilog; Use OVM (old) or UVM (new), eg., using Mentor Graphics extensive materials at the Verification Academy  https://verificationacademy.com/  Doulos has a nice UVM overview: http://www.doulos.com/knowhow/sysverilog/uvm/  3. MyHDL  Taking a conservative view; (1) and (3) are "projects" created by very talented individuals, but "individuals" none-the-less. If I had to consider long-term support and longevity, then SystemVerilog (2) would be the obvious choice (at least for me).  If I had time, I'd be interested in checking out all three options, but the reality is I do not, so I'll continue coding in VHDL, and reading SystemVerilog verification books to learn more :)  Keep up the interesting discussion ... :)  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Very nice discussion. I am all for HLS, and I am considering learning MyHDL.  --- Quote End ---    I missed this thread in February. I have done a major project with MyHDL: classification using support vector machines (http://en.wikipedia.org/wiki/support_vector_machine) I had been looking to MyHDL for several years, but never got round to do more than a lazy Sunday afternoon's play-session. But this year my favourite customer actually 'required' to do this project in MyHDL. And it was great. Of course a lot of the RTL coding stays along the same lines (there is no magic silver HLS). But what impressed me most is the ease of generating self-checking testbenches. You have all the power of Python and the libraries to generate test-data and monitor the results. Making writing extensive testbenches a lot less tedious.  MyHDL produces perfect VHDL (I haven't checked the Verilog code, as I wouldn't touch that even with a bargepole) not being rubbish as claimed by Tricky.  Learning Python is about the best thing any engineer can do. Apart from MyHDL I have used Python to write an Assembler for a specialised CPU, generated pdf documentation (using pyx and psfile), and even designed some 3D objects with it (SolidPython -> OpenScad).   Now there is still a lot of room for improvement for MyHDL and the developers are working on nice futures like fixed point and interfaces. There are a few touchy points as well. MyHDL treats Verilog and VHDL code generation equally, which is a limitation e.g. in VHDL you can do double (and triple and ...) arrays which Verilog doesn't. As Dave mentions including an external IP core is also not straightforward as you to need to write a Python model for it. But you don't need to do everything in one language, do you?  So by all means, try it out. If you need a little help or have a question, pop over to http://news.gmane.org/gmane.comp.python.myhdl A hint: use the pydev (http://pydev.org), sigasi (http://www.sigasi.com/) and impulse (http://toem.de/index.php/projects/impulse) plugins in eclipse (http://www.eclipse.org/) and you'll 'have done 500 miles today and even never left la'

[Altera_Forum]

Hi Josy, 

 Thanks for providing your positive impression of MyHDL.  At the last couple of Embedded Systems Conferences in San Jose, I chatted with Chris Felton who has also implemented major projects in MyHDL. Googling his name comes up with a few MyHDL tutorials that people can look at;  http://www.xess.com/blog/learn-fpga-programming-with-myhdl/ https://bitbucket.org/cfelton/pyohio http://www.fpgarelated.com/showarticle/25.php https://bitbucket.org/cfelton/  Cheers, Dave

[Altera_Forum]

Thanks Josy and Dave. 

 Going to try out MyHDL right now.  Cheers

[Altera_Forum]

So, I've have had some free time and decided to try out MyHDL. I am trying to re-write an ugly old module that I made 4 years ago when I was starting VHDL but I am struggling with synthesis. 

 It's working perfectly in Python! Here is my Py cordic code: http://pastebin.com/nzphemry and here is my testbench in Py: http://pastebin.com/ptqkwjn6 I do have a problem with the angle validation, The py function returns from -pi to pi and I have to do the same with my cordic, but I won't worry about that now.  So, I've generated the VHDL and compiled in my project, here is the VHDL: http://pastebin.com/5j5muvgq  Compared to my OLD VHDL ( http://pastebin.com/v9fjvuxr ), I do prefer the generated one, it uses less logic, the ports are smaller and it's also 1 uS faster (and I have python functions, yay). This OLD VHDL is really old, there are a few errors with it like mixing numeric_std and signed_artih, but...  the MyHDL VHDL isn't working in my product! :(  I know that's a lot of work, but I've been scratching my head and I can't find why the MyHDL VHDL isn't working. I am getting some random values from my acquisition board instead of the right mag/ang pair.  I've made a test bench with both VHDLs running in paralalel and I get the same result from both.  I don't know if it's a problem with the Variable usage or these cases returning a constant to a variable, or even the state machine being half if/else half case. Everything seems OK, I took a look at the RTL Viewer and didn't see anything strange.

[Altera_Forum]

--- Quote Start ---  So, I've have had some free time and decided to try out MyHDL. I am trying to re-write an ugly old module that I made 4 years ago when I was starting VHDL but I am struggling with synthesis.  It's working perfectly in Python! Here is my Py cordic code: http://pastebin.com/nzphemry and here is my testbench in Py: http://pastebin.com/ptqkwjn6 I do have a problem with the angle validation, The py function returns from -pi to pi and I have to do the same with my cordic, but I won't worry about that now.  So, I've generated the VHDL and compiled in my project, here is the VHDL: http://pastebin.com/5j5muvgq  Compared to my OLD VHDL ( http://pastebin.com/v9fjvuxr ), I do prefer the generated one, it uses less logic, the ports are smaller and it's also 1 uS faster (and I have python functions, yay). This OLD VHDL is really old, there are a few errors with it like mixing numeric_std and signed_artih, but...  the MyHDL VHDL isn't working in my product! :(  I know that's a lot of work, but I've been scratching my head and I can't find why the MyHDL VHDL isn't working. I am getting some random values from my acquisition board instead of the right mag/ang pair.  I've made a test bench with both VHDLs running in paralalel and I get the same result from both.  I don't know if it's a problem with the Variable usage or these cases returning a constant to a variable, or even the state machine being half if/else half case. Everything seems OK, I took a look at the RTL Viewer and didn't see anything strange.  --- Quote End ---    Hi Aprado,  I compiled your code too and as you say everything looks very much OK. If the code is not working in the 'real' FPGA you will have to use SignalTap to find the error ... One observation: if your result has a precision of 16 bits you can limit the 'num_iteracao' to 16 as the 8 remaining iterations will add 0 to the result. You can also gain one clock per iteration by testing 'num_iteracao' in state CALC_CORDIC_2 and then transition to a single final state to update the output and generate the 'finish_cordic' pulse.

[Altera_Forum]

Thanks Josy, it was indeed working. I had a problem with other modules because this one got faster, lol 

--- Quote Start ---  Hi Aprado,  I compiled your code too and as you say everything looks very much OK. If the code is not working in the 'real' FPGA you will have to use SignalTap to find the error ... One observation: if your result has a precision of 16 bits you can limit the 'num_iteracao' to 16 as the 8 remaining iterations will add 0 to the result. You can also gain one clock per iteration by testing 'num_iteracao' in state CALC_CORDIC_2 and then transition to a single final state to update the output and generate the 'finish_cordic' pulse.  --- Quote End ---  

[Altera_Forum]

I also did a simple UART design with MyHDL. It works just fine: https://github.com/andrecp/myhdl_simple_uart 

 :)  Cheers