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Altera_Forum
Honored Contributor I
1,764 Views

QIP File doesn't include the submodules after adding in a certain conneciton

Hello, 

 

I'm currently facing an issue with Quartus II Lite. I have a DE0-Nano-SoC board from terasic and I'm customizing one of the sample designs that they provide. I am struggling with an issue where I add in an APB translator and the QIP file removes the submodules. It only seems to do this once I export the slave connection.  

 

What I'm essentially trying to do is to expose an APB master interface and an additional APB slave interface to test out a custom made SPI block. My thought was to instantiate two APB translators in Qsys, expose the master interface of one of these, and the slave interface of the other to the top level, where I would then instantiate my SPI blocks. I could then issue memory accesses to my SPI master, and have the slave operate on memory inside the FPGA (through the on-chip ram as an example). My problem is, once I added these translators, the QIP file removed the inclusion of the various submodules. This causes the following error in compile: 

 

Error (12006): Node instance "u0" instantiates undefined entity "soc_system". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.  

 

 

My QIP file is only ~30 lines when I export the slave interface as an example. If I just let the interfaces float, the QIP file seems to be working, but obviously is not what I need. I have the QIP file included, but with it referencing nothing, it obviously doesn't do much good. I would think that I could add in each submodule file, but that seems to defeat the purpose of Qsys. 

 

 

Has anyone else seen something like this or know a possible solution? Even if there was a way to make the log more verbose when generating the Qsys system, I would like to see if I could chase it down that way. 

 

Thanks
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2 Replies
Altera_Forum
Honored Contributor I
339 Views

So you're just exporting these interfaces on the System Contents tab in Qsys? Under the Generate menu, does the instantiation template show the individual signals of the exported interfaces?

Altera_Forum
Honored Contributor I
339 Views

I was finally able to figure it out. What seemed to happen was, I was using an APB translator to interface with the AXI slave port on the HPS. I didn't select "USE_MADDR31" (or some parameter like that). My assumption is that it made a 31bit APB connection opposed to the desired 32 bit. I think that Qsys tried to do a interconnect block and just crapped out. However, it did not give any errors or warnings about it. I just happened to notice in the interconnect flow chart that there were two width interconnects. That didn't seem correct so I played around until I found that parameter. Once I set that, it seemed to resolve the issue.

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