Hi,I have followed the tutorial QSYS Avalon-MM Master BFM Tutorial for SystemVerilog and VHDL Testbenches: http://www.alteraforum.com/forum/showthread.php?t=48928 Which I got working and simulating fine. I am now trying to use what I learnt to run a simulation of my own logic in VHDL. I have set up my QSYS as per the attachment bfm.jpg I am using a bfm master to control the avalon mm slave components in the QSYS system. The aim of the simulation is to sample data from an ADC through a dcfifo connected as a streaming source, to a MM sram (using on chip memory for simulation) using a mSGDMA component. The adc_qsys and adc_sample are two user created components which I have simulated on their own and are functioning. My first question is: 1) Will connecting the streaming source of the ADC to the streaming sink of the mSGDMA and the mm master of the mSGDMA to the mm slave of the on chip ram simulate when I generate the qsys. Do I have to use another BFM for these paths? Assuming that the QSYS system I have put together is valid. I have generated the QSYS. I created a VHDL simple test bench based on the example test bench in the tutorial, see attached qsys_bfm_system_tb.vhd as its too long to put in post. So now I follow the tutorial: I open modelsim ASE, I change directory to ..\qsys_bfm_test_system\simulation\mentor. I run source msim_setup.tcl com vcom log_pkg and my testbench, which compile without any errors. set TOP_LEVEL_NAME to qsys_bfm_test_system_tb elab +nowarnTFMPC now here is where I get confused. The elab returns a lot of warnings about not bound components. see attached modelsim_lib.jpg note warnings component instance "adc_qsys : qsys_bfm_test_system_adc_qsys" is not bound component instance "adc_sample : qsys_bfm_test_system_adc_sample" is not bound I also get a load of warnings about mm_interconnect and dispatcher.v and some other stuff. Now in the library window I can see adc_qsys and adc_sample have been compiled into libraries named adc_qsys and adc_sample. The tutorial did talk about this, so I included a library definition in my test bench to include these:
LIBRARY adc_qsys; USE adc_qsys.adc_qsys.all; LIBRARY adc_sample; USE adc_sample.adc_sample.all;I also tried:
LIBRARY adc_qsys; USE work.adc_qsys.all; LIBRARY adc_sample; USE work.adc_sample.all;But both resulted in same set of warnings in modelsim. When I look in the sim window of modelsim I can see the bfm_master the sram and the mSGDMA but there isnt the adc_qsys or adc_sample component. see attached mdelsim_sim.jpg When I run the simulation it doesnt work as there are no signals for adc_qsys or adc_sample. 2) can anyone help me with what is going wrong? I am hoping its something simple like I am not including the correct library? do I need to copy the user vhdl into the same simulation folder and compile it seperately? Any help would be appreciated, Thanks James
When you simulate your Qsys system, all the files needed for simulation should ideally appear in msim_setup.tcl, eg., your ADC _hw.tcl components need to define the files required for simulation as well as synthesis.Quartus Qsys is a little annoying when it comes to getting all the simulation files correct. I'll often use my own pre-compiled libraries for components. In your case, just compile the missing components, eg., create the library and compile your ADC source vlib adc_qsys vmap adc_qsys ./adc_qsys vcom -2008 -work adc_qsys <adc VHDL filename> Once you eliminate the warnings about missing components, your simulation should run. At that point you could write your own sim.tcl script that calls msim_setup.tcl and compiles the stuff that Quartus misses. Cheers, Dave
Hi Dave,Thanks for replying about this. I am still having problems. I had a look at the msim_setup.tcl and it looks like the correct files are being compiled when I run the script. I also see them in a library in the modelsim window. I attempted to compile the library as you stated with vlib vmap and vcom but the not bound warnings persist when I run the elab. I have attached the msim_setup.tcl that was generated (with extension txt or it wouldnt upload), in the com function (line 173 and 174) there are vcom's for both adc files.
vcom "$QSYS_SIMDIR/submodules/adc_sample.vhd" -work adc_sample vcom "$QSYS_SIMDIR/submodules/adc_qsys.vhd" -work adc_qsysAre these incorrect? --- Quote Start --- your ADC _hw.tcl components need to define the files required for simulation as well as synthesis. --- Quote End --- Do I need to edit or include the *hw.tcl files somehow? To add to the confusion I noted in the component editor in qsys under files there is a VHDL Simulation Files window, do I need to have something in here? I have tried using the same file as the synthesis (there is a copy from synthesis files button) but this generates a warning the SIM_VHDL fileset must specify the top-level module name. There is also a simulation section in the qsys generate, do I need to use this? In the tutorial this wasnt required so im guessing I dont need to worry about either of these?
Note how your VHDL code gets compiled into a library that has the same name as the component instance. I find this a terrible feature of Qsys. If I create ADC code, and an ADC package, and then compile it into an ADC library, then my VHDL would have the lineslibrary adc; use adc.adc_pkg.all; In Qsys there is no easy way to specific the library in which to compile your ADC, i.e., there is no way to over-ride the -work argument it uses to the vcom command. The BFM tutorial appendix "complains" about this :) The _hw.tcl script should have a section for QUARTUS_SYNTH, VHDL_SIM, and VERILOG_SIM which lists of files to use during simulation. There is also a flag that can be used to allow mixed-mode simulation. If none of this makes sense, perhaps post your project code to this thread, or to me directly (to my forum name) and I'll try to take a look. Cheers, Dave
Hi Dave,I have had another go stripping out the simulation files into a seperate project and attempted your suggestions but I am still having problems. I have sent you an email with the project as I am still unable to get the test bench to find the user logic. Any help would be appreciated! Thanks James
Was this ever solved? I am having the same problem with unbound components (for ADC IP), Quartus creating libraries with the same name as ADC IP, etc. Pulling my hair out on this one, came to the forum looking for answers, and finding that most of these are unresolved or unpublished solutions.