Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Qsys Avalon bus symbol width

mke
Beginner
336 Views

Hi,

 

I have a question regarding the Avalon bus symbol width.

 

First, I have a custom IP with Avalon bus data width 576 bits. And I connected Avalon BFM to it in order to simulate it and here is where the problems begin.

 

First of all, the BFM does not allow any other "number of symbols" than the power of two: 32, 64, 128. Ok, this is fine. To achieve the 576 bits data width I changed the symbol width to 9 in BFM and also in my custom IP. So my custom IP has 576-bit data buses and 9-bit symbols: 576/9=64 symbols. And the same for the Avalon memory-mapped slave BFM: 64 9-bit symbols. Both, the slave BFM and my custom IP are using "WORDS" as the addressing unit. But Qsys keeps complaining that I can not connect buses with different symbol widths regardless I have the same symbol width set up for both. And it also complains that the master address range is insufficient.

 

So I made another simple system with two BFM-s, master and slave. And just connect those. If I use the symbol width 8 in both BFM-s everything is fine. But without changing anything other than the symbol width in both of the BFM-s to 9 the Qsys issues an error that the slave's address range is outside of the masters. Again, both BFM-s use exactly the same settings and everything is OK with the symbol width 8 for both.

 

So, question? Is there something that I overlook or maybe there is a bug in the Qsys while using some "custom" symbol width?

 

The Qsys version I'm using is 21.1 build 169, shipped with Quartus pro. And the project is targeting Arria 10 family.

 

BR, Madis

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4 Replies
mke
Beginner
319 Views

Additional:

 

I played a bit with the system with just two BFM-s connected together. If I use 8-bit symbol width, 64 symbols, 32-bit address, and addressing mode as "word" for both master and slave then everything is fine.

 

But if I change the symbol width to 9 (both master and slave) I have to use a 33-bit address for the master while the slave did not change, except the symbol width. Qsys complains about masters insufficient address range otherwise. Could you please explain to me what I am overlooking here?

 

BR, Madis

EBERLAZARE_I_Intel
263 Views

Hi,


Regarding the symbol widths:

Symbol width should be 1, 2, 4, 8, 16, 32, 64 (bits) Number of bits per symbol. This should apply to all.

If you use byteoriented interfaces it should have 8-bit symbols. 





EBERLAZARE_I_Intel
237 Views

Hi,


Do you require further help?


mke
Beginner
233 Views

Actually no, thanks. I exported the Avalon interfaces and did the connection outside of Qsys manually. Then everything was fine with 9-bit symbol width.

 

BR, Madis

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