Hi!
May be this is a simple question but I need help.
I used Qsys to create and generate a cpu then a test bench model for it (as explained on alterawiki).
Then I modified generated files and scripts to make a new top level file where I connect my cpu to some other logic components.
This top level block have now inputs that are directly connected to the cpu.
I read that in Qsys, I should use the option "Standard, BFMs for standard Avalon interfaces". Qsys generation ended with some warnings like ".... must be exported, or connected to a matching conduit."
So I went back to Qsys and "hardwired" all these inputs.
Now, in my new test bench I have the generated BFMs for all these inputs.
My question is how can I drive them?
For example I have:
coeff_1_external_connection_bfm inst_coeff_1_external_connection_bfm(
.sig_export (coeff_1) // conduit.export
);
Why when I set these inputs to some values, it didn't work (in a wave window, signals at top level are ok but at the cpu input are at 'X') ?
I searched the reason behind this, I saw that these BFMs use a system verilog model in which is defined some functions such as set_export().
Then I got confused, do I need to use these functions to set my sytem inputs?
Any help would be appreciated.
Thank you!
