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With a DE2i-150, I am trying to do fast matrix calculations between the Atom processor and the FPGA (for my own project/not for school work).
What I have right now is a modified DE2-i150_PCIE_Fundamental example design, where I can send user-defined data via a modified version of the corresponding VC++ code. I also have a custom implementation of Faddeev's algorithm (for pipelining matrix calculations) written in Verilog. the question I have is how to I take the sent data, process it, and send it back to the Atom. Essentially, I am trying to read from the onchip memory, and I want to know how to directly connect the data to the inputs of my Verilog file. The process I want to make looks as following: https://www.alteraforum.com/forum/attachment.php?attachmentid=9208 Thanks a lot. *it would also work if i could access the send data without storing in memory *also, sorry if my problem is too trivial, if i am unclear or sound rude, and/or if the question is a re-post.Link Copied
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use NIOS II in your QSYS design, write some firmware using NIOS II SBT, then load it onto your system. Let me know if these keyword helps.

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