Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Qsys component -- conduit_splitter clock setting

Altera_Forum
Honored Contributor II
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I added one more output to an previously 2-output conduit_splitter in Qsys. 

I keep getting the error saying the added conduit_output has no associated clock 

But I don't see any clock settings available at the conduit_splitter component from the library. 

 

The way I added the output signal is simply change the parameters of output numbers of the conduit_splitter. I didn't modify any of the original design files. And also there are no errors regards the other two output signals. 

Aren't all the three output signals supposed to be the same since they are merely splitted from the same signal? 

 

Does anyone have similar problem with conduit_splitter clock settings? 

 

I use Quartus II 13.0, Qsys 

 

Any advice will be appreciated. 

Thank you.
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Altera_Forum
Honored Contributor II
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I got the answer. 

For those who have similiar problem, the conduit_splitter from Altera's reference design is not supposed to used by customers. Therefore, they don't have clock and reset settings in the conduit_splitter component. Anyone who wants to have a conduit splitter can simply add the clock and reset interface on the original one.  

And also the clock and reset setting of the connection interface on the other component need to match the concuit clock and reset setting. 

 

I hope it helps.
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