Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Qsys component

Altera_Forum
名誉分销商 II
2,591 次查看

Hello  

I try to add new componet to Qsys 14.1. The component file attached. The error occor is "Error: There are multiple signals with role "export". Components using hw.tcl package 14.0 and greater must specify unique signal roles. 

while executing 

"add_interface_port export_s1 avs_s1_export_capture_read export Output 1" 

 

How to solve this problem? 

Thanks
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Altera_Forum
名誉分销商 II
669 次查看

Hello, 

 

I think there is some problem in hw_tcl file and not in your verilog file. You should check that TCL file. Could you upload that file here? 

 

Cheers, 

Bhaumik
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Altera_Forum
名誉分销商 II
669 次查看

Thanks for reply  

Tcl file uploaded. 

Thanks alot
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Altera_Forum
名誉分销商 II
669 次查看

Hi, 

 

Following thread given me hint : http://www.alteraforum.com/forum/showthread.php?t=29684 

 

I have made changes for that and now that error has disappeared. Please try with attached TCL file and let us know output. 

 

Cheers, 

Bhaumik
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Altera_Forum
名誉分销商 II
669 次查看

Hi  

Thanks Dear Bhaumik
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