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Hello
I try to add new componet to Qsys 14.1. The component file attached. The error occor is "Error: There are multiple signals with role "export". Components using hw.tcl package 14.0 and greater must specify unique signal roles. while executing "add_interface_port export_s1 avs_s1_export_capture_read export Output 1" " How to solve this problem? Thanks
CMOS_Controller.v
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Hello,
I think there is some problem in hw_tcl file and not in your verilog file. You should check that TCL file. Could you upload that file here? Cheers, Bhaumik- Mark as New
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Thanks for reply
Tcl file uploaded. Thanks alot
CMOS_CONTROLLER_hw.zip
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Hi,
Following thread given me hint : http://www.alteraforum.com/forum/showthread.php?t=29684 I have made changes for that and now that error has disappeared. Please try with attached TCL file and let us know output. Cheers, Bhaumik
CMOS_CONTROLLER_hw.zip
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Hi
Thanks Dear Bhaumik
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