As elsewhere I have a CIV hard IP based PCIe design based around a Qsys implementation of the PCIe core and a 'component' encapsulating my custom logic.
When this is built under Quartus 11.0 things work well, we're getting data DMA'd to the host memory as expected. The only problem is that PCIe interrupts are broken in Q11.0.
The Qsys component was initially created in Quartus->Qsys 11.0
If I open the project in Quartus 11.1 sp2 then open Qsys, regenerate the qsys system then rebuild the FPGA we are seeing problems with missing data in the target memory. The missing data is ~ 1 in every 40 32 bit words transferred.
I'd have expected the project to behave the same way under 11.0 and 11.1 sp2 (except the interrupts would work).
Do Qsys components have to be rebuilt for newer versions of Quartus/Qsys?
Thanks for any feedback.
Nial.
