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RS232 rxd code

Altera_Forum
Honored Contributor II
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Hi :) 

 

i'm new here and i need some help... 

 

i work on project and i need to read from kind of machine some letters... there is an ascii code to all letter. this machine send words that i need to read them. in this words i need to check the letters (Y/N)? 

for the start of this check i want to check one letter/char for example: ( or Y or / . 

i know that machine send '1' (idle) always and when i press "reset" on this machine, the machine send words that i need to read with start bit+8 bits (data)+stop bit. 

 

I'll be glad if someone would help me to write this code or give me examples of rxd codes :) 

 

thanks...
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Altera_Forum
Honored Contributor II
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Start by drawing your design. The www can help you. Use your favorite search engine and search for UART or rs232.

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Altera_Forum
Honored Contributor II
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Probably further details ie block diagram would be helpful to illustrate your target implementation.

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Start by drawing your design. The www can help you. Use your favorite search engine and search for UART or rs232. 

--- Quote End ---  

 

 

 

--- Quote Start ---  

Probably further details ie block diagram would be helpful to illustrate your target implementation. 

--- Quote End ---  

 

 

this is my code (out1 is clock 9600 from component that conected to this component code): 

 

library ieee; use ieee.std_logic_1164.all; --here, there is one more "use ieee" that i do not remember (not numeric) entity rxd is port( out1: in std_logic; --clock 9600hz rxd: std_logic; led: std_logic; --to check if the data "00111111" is recieved ); end entity; architecture arc_rxd of rxd is signal cnt: integer:=0; --to check the 8 bit of data signal word: std_logic_vector(7 downto 0); --to put the data in signal type state_type is(start_bit,check_bits,stop_bit,data_out); signal state: state_type; begin process(out1,rxd) begin if(out1='1' and out1'event)then case state is when start_bit => if(rxd='0')then -- check start bit state<=check_bits; elsif(rxd='1')then state<=start_bit; end if; when check_bits => cnt<=cnt+1; if(cnt<8)then word(cnt)<=rxd; elsif(cnt=8)then state<=stop_bit; cnt<=0; end if; when stop_bit => if(rxd='1')then state<=data_out; end if; when data_out => --this state check if the data "00111111" is recieved if(word="00111111")then led<='1'; else led<='0'; state<=start_bit; end if; end case; end if; end process;  

 

i get the data from mvme162... on hyper terminal i see words that mvme162 transmit... i need to check if the letter/char "?" is there.. if is there led<='1'... (?=00111111 in ascii).
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Altera_Forum
Honored Contributor II
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Then you compare the received bits with a bitmask for your char. Or am I missing something?

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Altera_Forum
Honored Contributor II
1,027 Views

 

--- Quote Start ---  

Then you compare the received bits with a bitmask for your char. Or am I missing something? 

--- Quote End ---  

 

 

yes... for example: the code ascii of letter "Y" is "01011001" by ascii table... and if mvme162 transmit the letter "Y" so the led<='1', but then i the code in the altera (cyclone ii) the led is always '0' and noything cahange... and i can see that mvme162 transmit.
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Altera_Forum
Honored Contributor II
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Have you run a simulation?  

Have you verified the reiceiver works as expected? 

I assume you always check in the middle of the bit?
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Have you run a simulation?  

Have you verified the reiceiver works as expected? 

I assume you always check in the middle of the bit? 

--- Quote End ---  

 

 

yes 

yes by c# and work perfect... i think is about a lot of bits are sent... 

Hmm...how do i check in the middle of the bit?
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Altera_Forum
Honored Contributor II
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The bit takes time to send. So you need to check your bit in the middle of that duration so you know for sure what bit you read. On the edges gives inacurate readings. Also, you need to pass your signal trough a synchronizer to prevent metastability.  

Back to read in the middle: Once you detected the start bit (first falling edge after stopbit) you wait half the bittime and than start reading.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

The bit takes time to send. So you need to check your bit in the middle of that duration so you know for sure what bit you read. On the edges gives inacurate readings. Also, you need to pass your signal trough a synchronizer to prevent metastability.  

Back to read in the middle: Once you detected the start bit (first falling edge after stopbit) you wait half the bittime and than start reading. 

--- Quote End ---  

 

 

how do i check i the middle? can you help me? if you can to take my code and show me how to check in the middle :) thanks
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

 

Back to read in the middle: Once you detected the start bit (first falling edge after stopbit) you wait half the bittime and than start reading. 

--- Quote End ---  

 

 

I would use a timer for waiting, and add a state to check the timer.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

I would use a timer for waiting, and add a state to check the timer. 

--- Quote End ---  

 

 

can you show me how?
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Altera_Forum
Honored Contributor II
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I could, but there is enough reference material on the www. Use your favorite search engine and search for VHDL Timer.

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Altera_Forum
Honored Contributor II
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You might think about changing the clock and use the wait timer to also time the bits.

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Altera_Forum
Honored Contributor II
1,027 Views

 

--- Quote Start ---  

I could, but there is enough reference material on the www. Use your favorite search engine and search for VHDL Timer. 

--- Quote End ---  

 

 

 

--- Quote Start ---  

You might think about changing the clock and use the wait timer to also time the bits. 

--- Quote End ---  

 

 

its work :) rx was connected to rx and tx was connected to tx but its work just if rx to tx and tx to rx (wires)... 

 

thank you all :)
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