Qsys custom component generation callback issue

[Altera_Forum]

I have a few custom Qsys components where I generate the final VHDL source to be included from a template file using the generation callback. The generation consists of omitting input and output port signals., e.g. remove the channel info from the stream. Now if I use a component multiple times in a Qsys set-up, the generation will produce sub-module files where the previously generated source precedes the actual generated code. So if e.g. I use the component three times, the first generate file holds a single entity, the second will get two entities, and the third three (and so on ...). You can see the effect in the attached files. I also attach the hw.tcl file for the experts. The attached image shows that the generation writes the same amount of lines for both instances, yet for the second instance the result shows that it is a concatenation of the previous one with the actually generated.

[Altera_Forum]

I searched further in my code, and yes it is in the code (as it (999 out of a 1000 times) always is ...). To do the deletion of the lines I split the read source VHDL file into a list of lines and then ran through each one deciding to append it it another list. Here I got caught by the 'persistence' of Tcl variables. I declared that list as a variable. The Qsys generation process calls my generation routine in the same 'context' and as a result I appended the new source to an existing list holding all previously appended lines. So I now declared an empty list -> problem solved. I attach the modified Tcl code for the interested readers.