Qsys error : has write interface but no write control

[Altera_Forum]

Hi , I am trying to create a new component on Qsys , using my verilog code. The problem is that after I select the interfaces and the kind of signals , an error :"Has written interfaces but not write control" appear on component editor, and I don`t know how to fix it. 

Anyone has some idea? http://www.alteraforum.com/forum/attachment.php?attachmentid=11113&stc=1  module count_freq( clk, asi_clk_50, test_pin, camera_clk, reset, sel , count); input clk, reset; input asi_clk_50, camera_clk, test_pin; input sel; output count ; reg count, count_next ,count_camera, count_camera_next, count_50, count_50_next, count_test_pin, count_test_pin_next ; always@ (posedge camera_clk or posedge reset ) if (reset) count_camera<=0; else count_camera<= count_camera_next; always@ (posedge asi_clk_50 or posedge reset) if (reset) count_50 <=0; else count_50<=count_50_next; always@ (posedge test_pin or posedge reset) if (reset) count_test_pin <= 0; else count_test_pin<= count_test_pin_next; always@ (count_50 or sel) if (sel==0) count_50_next= count_50+1; else count_50_next= count_50; always@ ( count_test_pin or sel) if(sel==2) count_test_pin_next= count_test_pin+1; else count_test_pin_next=count_test_pin; always@ (count_camera or sel ) if (sel==1) count_camera_next= count_camera+1; else count_camera_next=count_camera; always@( posedge clk ) if( sel==0) count<= count_50; else if (sel==1) count<= count_camera; else if (sel==2) count<= count_test_pin;

[Altera_Forum]

you have set asi_clk_50, test_pin, camera_clk and sel to avalon_slave_0 which is an altera defined interface for memory mapped components, see: 

 https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf  and as such has to obey the format defined in the document. you have set the signal type to writedata for 4 of the inputs and only 1 writedata is used in an avalon slave interface. hence the warning and a write signal is required with writedata hence your error.  this doesnt look like what you are trying to achieve. perhaps see the avalon conduit interface? also check the interface tab where you can set it all up using the gui

[Altera_Forum]

Thank you for your reply, I am new with Altera FPGA`s and I am a bit confused...I read something about avalon conduit interface, you are suggesting me that conduits can be used in my system in place of avalon memory mapped interafaces?

[Altera_Forum]

a memory mapped interface would be used when you are trying to write data using an avalon bus to a memory location in your component. An example of the type of inputs and outputs for an memory mapped interface would need : clk, reset, address, write, writedata, read, readdata, waitrequest, readdatavalid etc. 

 This doesnt look like what you are trying to do. Quote from the pdf i linked:  "Avalon Conduit interfaces group an arbitrary collection of signals. You can specify any role for conduit signals. However, when you connect conduits, the roles and widths must match and the directions must be opposite. An Avalon Conduit interface can include input, output, and bidirectional signals. A module can have multiple Avalon Conduit interfaces to provide a logical signal grouping. Conduit interfaces can declare an associated clock. When connected conduit interfaces are in different clock domains, Qsys generates an error message"  If you just want your signals passed in and out of your component in your own way then perhaps a conduit would be appropriate.

[Altera_Forum]

Ok thank you now is clear.