Qsys mm_interconnect - how to control size

[Altera_Forum]

I've got a largeish QSYS system with HPS and VIP suite modules, some dual-port RAM, etc. I've got a JTAG-MM Master hooked up to the control ports of the VIP modules, and I've got the HPS LW_AXI hooked up to those same control ports and some of the dual-port RAM. When my QSYS system is built, I get 5 mm_interconnect modules, and 4 of them are some 300-600 ALMs and the 5th is nearly 4000 ALMs. I've got them all clocked with the same clock, but for some reason this interconnect needs to take up a large percentage of my chip which I can ill afford. Would it be better to use the full AXI bus, not the lightweight one? 

 Cheers, Simon

[Altera_Forum]

Qsys generates logic for every interconnection, and if you connect dissimilar masters to the same slave, the logic at each connection point can explode. 

 Try inserting a pipeline bridge such that all your slaves have only the pipeline bridge as a master, and then connect your masters to the pipeline bridge.  I believe this is detailed in an appnote describing how to optimize Qsys designs, but I can't find the reference at the moment.

[Altera_Forum]

Thanks Ted, that's exactly what was required. Saved 3k ALMs!

[Altera_Forum]

--- Quote Start ---  I believe this is detailed in an appnote describing how to optimize Qsys designs, but I can't find the reference at the moment.  --- Quote End ---    Do you have this app note somewhere available?

[Altera_Forum]

Turns out it is in the Quartus Handbook, not an appnote - see the section "Creating Dedicated Master and Slave Connections to Minimize Interconnect Logic" in Chapter 8 Optimizing Qsys System Performance of https://www.altera.com/en_us/pdfs/literature/hb/qts/qts-qps-5v1.pdf  

 The entire chapter is worth a read if you're spending any time with Qsys.

[Altera_Forum]

Thanks I will have a deeper look into it.