Qsys : using pll locked conduit as a reset

[Altera_Forum]

Hi everyone, 

  I'm facing a little problem but it's very annoying.   I have implemented a QSYS system with a PLL and a NIOS2 processor. The processor is run by a clock generated by the pll and I'd like to use the "locked" signal of the pll as a reset.   But locked is a "conduit" interface which is not compatible with a "reset" interface. I havn't found any component to change a signal from conduit to reset. So I have made one myself which simply assign an input conduit on an output reset:   entity q_conduit_to_reset is port ( conduit : in std_logic; reset : out std_logic ); end q_conduit_to_reset; architecture vhdl_rtl of q_conduit_to_reset is begin reset <=conduit; end architecture vhdl_rtl;    # # module conduit_to_reset# set_module_property DESCRIPTION "" set_module_property NAME conduit_to_reset set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property GROUP "My IPs" set_module_property AUTHOR "" set_module_property DISPLAY_NAME "Conduit To Reset IP" set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property REPORT_TO_TALKBACK false set_module_property ALLOW_GREYBOX_GENERATION false set_module_property REPORT_HIERARCHY false # # file sets# add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL q_conduit_to_reset set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false add_fileset_file q_conduit_to_reset_ip.vhd VHDL PATH ../hdl/vhdl/q_conduit_to_reset_ip.vhd TOP_LEVEL_FILE add_fileset SIM_VERILOG SIM_VERILOG "" "" set_fileset_property SIM_VERILOG TOP_LEVEL q_conduit_to_reset set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false add_fileset_file q_conduit_to_reset_ip.vhd VHDL PATH ../hdl/vhdl/q_conduit_to_reset_ip.vhd add_fileset SIM_VHDL SIM_VHDL "" "" set_fileset_property SIM_VHDL TOP_LEVEL q_conduit_to_reset set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false set_fileset_property SIM_VHDL ENABLE_FILE_OVERWRITE_MODE false add_fileset_file q_conduit_to_reset_ip.vhd VHDL PATH ../hdl/vhdl/q_conduit_to_reset_ip.vhd # # display items# # # connection point conduit# add_interface conduit conduit end set_interface_property conduit ENABLED true set_interface_property conduit EXPORT_OF "" set_interface_property conduit PORT_NAME_MAP "" set_interface_property conduit CMSIS_SVD_VARIABLES "" set_interface_property conduit SVD_ADDRESS_GROUP "" add_interface_port conduit conduit export Input 1 # # connection point reset# add_interface reset reset start set_interface_property reset ENABLED true set_interface_property reset EXPORT_OF "" set_interface_property reset PORT_NAME_MAP "" set_interface_property reset CMSIS_SVD_VARIABLES "" set_interface_property reset SVD_ADDRESS_GROUP "" add_interface_port reset reset reset Output 1    To have a good reset behavior, I use the "Reset Bridge" IP with the "deassert" option ON. I connect "locked" and "conduit" together. And I connect both reset together. Now I have the error "Synchronous edges DEASSERT requires associated clock".   I understand why I have this error and I can manage to remove it by adding the clock in my custom component. But there is something I cannot understand :   It takes A LOT OF ENERGY just to use the locked signal from a pll as a reset in a qsys system. I assume I have missed something and I'd like to know how you people are doing this stuff.   Thanks Aurélien

[Altera_Forum]

Hi Aurélien 

 A "quick and dirty" workaround to this problem would be bringing out your conduit signal outside of Qsys and wiring it to the reset input. That'd require adding two more Qsys ports: reset input and conduit output.  Thanks, Evgeni

[Altera_Forum]

--- Quote Start ---   It takes A LOT OF ENERGY just to use the locked signal from a pll as a reset in a qsys system. I assume I have missed something and I'd like to know how you people are doing this stuff.   --- Quote End ---   Ha! Yes, I experienced the same frustration recently. My solution was to simply remove the PLL from the Qsys system and move it to the top-level of my design, i.e., my top-level HDL file instantiates the PLL, PLL locked synchronization and the Qsys system. The PLL clock and reset signal derived from the synchronized PLL locked signal were then the clock and input signal to the Qsys system.  The example design is in this thread: http://www.alteraforum.com/forum/showthread.php?t=45927  Here's the top-level code:  -- ------------------------------------------------------------ -- PLL -- ------------------------------------------------------------ -- u1: pll port map ( areset => (not ext_rstN), inclk0 => clkin_50MHz, c0 => clk, c1 => sdram_clk, locked => pll_locked ); -- ------------------------------------------------------------ -- Reset synchronizer -- ------------------------------------------------------------ -- u2: sync generic map ( RESET_STATE => '0', PIPELINE => 2 ) port map ( clk => clk, rstN => (ext_rstN and pll_locked), d => '1', q => rstN ); -- ------------------------------------------------------------ -- Qsys system -- ------------------------------------------------------------ -- u3: qsys_system port map ( clk_clk => clk, reset_reset_n => rstN, sdram_cs_n => sdram_csN, sdram_ras_n => sdram_rasN, sdram_cas_n => sdram_casN, sdram_we_n => sdram_weN, sdram_cke => sdram_cke, sdram_addr => sdram_addr, sdram_ba => sdram_ba, sdram_dqm => sdram_dqm, sdram_dq => sdram_dq );   Cheers, Dave

[Altera_Forum]

Hi guys and thanks for your reply. 

I was already aware of these workarounds and I was searching for some better solutions but obviously, there isn't any !  If an altera worker see this thread, I just want to say that PLL locked signals are always used as reset, and it's just not understandable that qsys do not allow this behaviour.  Cheers, Aurélien