Qsys

[Altera_Forum]

As you find workarounds to Qsys issues please add them to the list found here: http://www.alterawiki.com/wiki/new_qsys_issues 

 You'll save others some time and your input will be monitored by Altera as well.  If you require assistance from Altera tech support please file a service request at this link: http://www.altera.com/mysupport

[Altera_Forum]

Hi BadOmen, 

 I've just posted a tutorial on how to use the JTAG and BFM Avalon-MM masters from SOPC and Qsys. There were a few problems experienced during the development of the tutorial that I have noted in an appendix  http://www.alteraforum.com/forum/showthread.php?t=34787  http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.zip)  Could you please take a look at the tutorial and then forward the list of problems to the appropriate people within Altera. A similar list of issues was made when looking at the JTAG-to-Avalon-MM bridge implementation. Perhaps you could also forward that information too.  http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_jtag_to_avalon_analysis.zip)  Posting an Altera Service Request for this sort of detail hasn't proven to be particularly effective for me in the past.  Cheers, Dave

[Altera_Forum]

I forwarded this post along to the group that handles Qsys and the JTAG-to-Avalon bridge. By the way, if you filed SRs on these and they went nowhere, go head and PM me the service request numbers I'll ask the individual to take a closer look.

[Altera_Forum]

--- Quote Start ---  I forwarded this post along to the group that handles Qsys and the JTAG-to-Avalon bridge.   --- Quote End ---  Thanks!    --- Quote Start ---   By the way, if you filed SRs on these and they went nowhere, go head and PM me the service request numbers I'll ask the individual to take a closer look.  --- Quote End ---  The tutorial is hot-off-the-press so I didn't file an SRs related to these issues. As you can see from the tutorial, there are work-arounds for everything. The issues raised are mostly related to tool improvement.  The last SR I submitted was related to the Verification IP suite. I never received a response to it, so I posted to the forum.  http://www.alteraforum.com/forum/showthread.php?t=26957  I guess the issue was a little obscure, given that noone responded here either :)  Cheers, Dave

[Altera_Forum]

As elsewhere I have a PCIe system that's been working unde Quartus 11.0 but interrupts are broken there so I tried to build it in Quartus 11.1 sp2 and got an Error (10232) or Error 10232 (to help further searches). 

 I put this down to differences in Qsys versions but tried a fresh build under 11.1 and got the same problem so raised an SR. There is mention of this same error about with a fix (enclosing it in a wrapper) but I was seeing this in multipe places in Qsys generated files so that wasn't an option.  I've included details here in case it helps anyone else..... >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> My problem.... I am building a fresh design in Quartus 11.1 sp2.  When I intially try to run Quartus I am getting Error (10232) as above. This is on a Qsys generated file.  I have had an exact copy of this system working under Quartus 11.0, the PCIe interrupts are broken there so I need to get it building under v11.1. >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> The Fix:  This is a known issue to our software engineering team.  We have identified the root cause of the problem which is related to master address width limitation.   The workaround for this issue is to put the slave at a higher base address to force the master's address width to increase.  For example, you can set the base address of the pio_0.s1 component to 0x00050000-0x0005001f (please see the attached screenshot for the details illustration).  This will force the address signal of the bar1_0 master to increase, Regenerate Qsys and recompile in Quartus v11.1sp2, the error will disappear.  I am sorry for the inconvenience caused. This problem will be fixed in the future Quartus II software release.

[Altera_Forum]

Hi 

I have a problem with the QSYS in Quartus II Version 12.  When i open my custom ip core in qsys, by right click -> edit, and then save the .tcl without making any changes, all 'add_fileset_file' entries in the tcl file are deleted, except the one for the top level file. What is the reason behind this and how can i fix it?   Thanks and best regards Chrigu

[Altera_Forum]

chrigu, 

 I have the same problem and I submitted an SR on this and Altera has acknowledged that it is a bug. This bug will be fixed in version 12.1 due out this fall/early winter. The workaround is to add all the files once to the custom component and then only update the component editing the _hw.tcl file manually.   I found another issue with the component UI in qsys and that as well has been submitted and they can verify that it is a problem. If you add a .qip file to the fileset of a custom component once you generate the system in qsys and then compile it in Quartus. Quartus will not find the files that the .qip file points to since it relies on relative paths to where the .qip file is located and during qsys generation the .qip file is copied to a qsys system directory.   /Boris

[Altera_Forum]

Hey Boris,  

Thanks for your answer. Yes, editing the files manually seems to be the best way.  Greets Chrigu

[Altera_Forum]

I am having some issues with using the MP32 soft core in the Quartus 11.1 software. Apparently the solution to fix this is to downgrade from 11.1 to 10.1. Is there any way how to fix this problem without downgrading? 

 Also does anybody know of any good tutorials of interfacing with Avalon-MM?(Master and Slave)

[Altera_Forum]

Without knowing the issue it'll be hard for others to give advice on workarounds. 

 For tutorials do you mean how to integrate a system that uses MM or something specific to designing Avalon-MM masters and slaves? If it's the latter I would start with becoming familar with the Avalon-MM specification (make sure you read version 2.0 if you use Qsys). You might find the easiest way to learn the implementation is to look at some 'clean' HDL. If you look at the memory tester blocks in the Qsys tutorial that might give you some ideas on how to structure your logic.

[Altera_Forum]

I am looking for a tutorial that teaches you how to design components that uses the Avalon-MM interface. I am planning to use it in QSYS. There are two components I need to interface currently with Avalon-MM. One is a CPU similar to Nios-2, and the other is a VGA controller that uses DMA to access the SDRAM to retrieve the RGB values for each pixel. 

 I will look into the memory tester example. I didn't pay too close attention to it so I guess there may be some code that lets me see the interfacing happen.  EDIT: The memory tester example is in verilog and uses C code so I can't use that as an example.

[Altera_Forum]

There used to be an EMIF SOPC Builder example that showed connecting a TI DSP up to an Altera FPGA but I'm not sure where it went. It sounds like you want your processor to use a more native solution using Avalon-MM (or maybe AXI if you have the latest version of Qsys installed). That memory tester design also works with .tcl running the host machine which controls all those tester blocks (instead of running software on the Nios II core). I was only suggesting to look at the master logic to see how it's structured and what sorts of things you need to do to ensure compliance with the Avalon-MM specification. 

 If you are not interested in verilog or C, are you looking for a VHDL and assembly coded sample? I guess I'm not really following what you are looking for because interfacing to other Avalon based cores is just a matter of following the Avalon specification when you define your interface. So if you have a customer processor it will have some sort of interface and you just ensure it conforms to Avalon-MM by adding a little glue logic if necessary.

[Altera_Forum]

I found myself an example here so I should be fine. I know that I had to follow the Avalon specification however I prefer an example so that I can be certain on how the implementation works.  

 Here is the example ftp://ftp.altera.com/up/pub/altera_material/11.1/tutorials/making_sopc_builder_components.pdf

[Altera_Forum]

Some general observations: 

 1) I don't recommend using chip select to qualify reads and writes (just use 'read' and 'write' for that)   2) That coding style probably doesn't scale to multiple registers very well. What I typically do is put the address decoding and byte enable and write qualification into one spot and when I need more register just replicate that one-liner.   3) For reads I wouldn't bother qualifying the byte lanes with enables, just register the entire word (master will have to filter out the unused byte lanes anyway...)   For masters whenever possible try to decouple the control and data paths. For example if your master is capable of issuing multiple reads try to minimize the amount of control logic that captures the read data. In my various DMA master implementations I typically do this by using a FIFO and the only interaction between it and the control logic is that the FIFO full, empty, and used signals are used to throttle the control logic. You mentioned you were looking to do video, search for "Modular SGDMA Video" on alterawiki.com and you should find a dirt simple implemenation of a video pipeline that is capable of re-displaying frames when there are no more frames available to display (in video you have to keep displaying otherwise your display will loose sync).

[Altera_Forum]

ModelSim and filename length limit  

 See this thread:- http://alteraforum.com/forum/showthread.php?t=37564

[Altera_Forum]

Hi 

I have a problem with the QSYS in Quartus II Version 13.1  When i generate my design the VHDL file is genarated. The problem is the assigments of the componenents greated by qsys are not all correct. It seems it randomly connects components.  spipiggy : component LSA_version_2_spiCurrentDac timersupsolv3pump : component LSA_version_2_timerOutNdlWashPump uartusb : component LSA_version_2_uartEthernet  is this a BUG ?

[Altera_Forum]

Hi, I use Qsys a lot with same components which have different generics. On some configuartions I've error during synthesis with  

error message which is coming from assertion in generated files:   ... assert false report "Supplied generics do not match expected generics" severity Failure;  I've googled for the error message and found exactly ONE site where this problem and ugly workaround are described. Is this issue fixed in newer Qsys versions? The site with problem description is here: http://flink-project.ch/multiple_subdevices_with_the_same_number_of_ports

[Altera_Forum]

Hi alex 

 you may add some property to the parameter, e.g.:  set_parameter_property <your parameter> AFFECTS_GENERATION false  this should end up in also just one file for the different variations of your generics...

[Altera_Forum]

Thank you for the hint. If this parameter is set to false, there is no "assert" statement generated for this parameter. If the parameter is the only one which is conflicting it solves the problem temporarily. This workaround also lasts only until next click on "Analaze Synthesis Files" in component editor: The _hw.tcl file is generated from scratch so all manual changes are lost. 

In my opinion this is still a bug in Qsys: each instance must have own vhd file if instances have changes on parameters for which "assert" statements are generated.

[Altera_Forum]

It would also be a good feature of component editor if this settings can be set by checkboxes in the "Parameters" tab and saved.

[Altera_Forum]

Unsticking this thread since Qsys has been available for years.