- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I used to debug my designs with a .vwf file. With Quartus II - v9 one can create a vwf file with Menu/New/Other files/Vector Waveform file. I can't find it in the new version of Quartus. Could anyone help me? Thanks :)Link Copied
6 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
They removed the simulator in Quartus 10. They expect you to either use modelsim or some other simulator now..
Pete- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
For a beginner who has only used vwf is there a good (simple) tutorial or similar info to get started with modelsim? There is a lot of small detail to try to remember in Q II and it is challenging until habit takes over.
Jack- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I hav e installed the ModelSimAltera Starter edition (v10.0c) with Quartus 11.1 and it seems to have no waveform drawing functions. In terms of quickly verifying function and timing it is WAY WORSE than the old built in simulator. What is going on?
Am I missing sometrhing in editing those waveforms.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
ModelSim + Testbench
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Writing a testbench can be done just as quickly as creating a waveform.
HDL is WAY more powerful for verification overall.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I Agree with tricky. A test bench is the way to go.
Learning Verilog or VHDL will be a great help both in your design and test bench. I have a simple "CPU" emulator (since most of my designs have a external CPU in the system), that I use over and over again. It simply reads a hex file for some simple functions (Read/Write registers, wait for signal, etc) If you want, you could have a hex file that simulated all the inputs to the chip and use it like a vector waveform. In verilog, the $readmemh is the command to look into. Pete
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page