Quartus 2-The hardware resource report in Compilation Report

[Altera_Forum]

Hi everyone, 

I'm now using two different methods to implement an algorithm on FPGA and I'd like to see the hardware resource consumption of each method. I compiled each program and the Compilation Report lists a lot of things which confused me a lot. Taking the Stratix ii family as example, the report will list how many Combinational ALUT's , Dedicated logic registers, Total registers, Total block memory bits ,DSP block elements this program costs. I wonder if there's a standard measurement for those hardware.I can translate different kinds of cost into one. Say X,then the ALUT = 2X, dedicated logic register = 3X .......DSP block element = 10X for example . In this way I can compare two methods hardware consumption easily.   Thanks a lot:)

[Altera_Forum]

The parts cannot be interchanged. Usually, LUTs and Registers are not so important as memories and DSP blocks are usually consumed first. But it depends which metric you are most interested in.

[Altera_Forum]

Thanks Tricky 

I'm not familiar with the structure inside the FPGA. However, even the Compilation Report lists a lot of different hardware cost, I think they are comprised of the basic unit inside the FPGA( cmos? gates? whatever......╮(╯▽╰)╭) . My point how can I get the basic unit cost (if it exists......).

[Altera_Forum]

The basic resources are LUTs and registers. The luts contain the basic gates that make up a functioning design. Registers are registers.  

DSP slices are special blocks containing multipliers and a few pipeline registers. Memories are what they say.   There is no basic unit cost. The question is does the design meet your timing constraints? does it fit any with any other logic in there? A basic logic count doesnt really have much meaning. A design could be tiny but really slow, whereas a larger design may operate much faster. Its all down to what your requirements are.