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Quartus 20.1.0 Synthesis of System Verilog Interfaces

bitstreamer
Novice
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I have basic interfaces with modports as below:

 

interface if_memory (
);

logic valid;
logic strobe;
logic wren;
logic [31:0] address;


modport client (
input valid,
output strobe, wren, address
);

modport host (
output valid,
input strobe, wren, address
);

endinterface

when I synthesize these interfaces connected between modules, I get the following warning:

Warning (12158): Entity "if_memory" contains only dangling pins


 I connect these interfaces using the following basic assignments

if_memory if_memory();
assign some_strobe = if_memory.strobe;
assign some_wren = if_memory.wren;
assign some_address = if_memory.address;
assign some_valid = regs_to_pkt_valid;

 

With the some_block using the interface:

 

some_block some_block (
...
.if_memory(if_memory.client),
...
);

 

With some_block as 

module some_block (

...
// memory interface
if_memory if_memory,
...
);

I've also tried if_memory.client as the port declaration, and passing in if_memory.


What is going on here? The only interfaces that do not have this dangling issue are clocked interfaces. 

 

Also, where are the system verilog capabilities for 20.1.0 that were last present in documents for 17.0?

 

Note that what I have above matches Intel examples for interfaces - is there some setting that I am missing?

 

 

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RichardTanSY_Intel
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This case will be closed because it was duplicate with an existing case. Please refer to the case below (link attached) for further support.

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Quartus-20-1-0-Synthesis-of-System-Verilog-Interfaces/m-p/1283669#M69392


Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

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