Hi all,
I am compiling a sample AES program from the book Design Recipes for FPGAs by Peter Wilson. However, it took four hours to compile the two files. Here's the message from Quartus II: Info: Started Full Compilation at Mon Oct 26 16:11:22 2009 Malay Peninsula Standard Time Info: Ended Full Compilation at Mon Oct 26 20:27:12 2009 Malay Peninsula Standard Time The example given use a package approach with a suite of VHDL functions rather than the structural approach. Can any one suggest a faster setting for compilation? Cheers, Dennis链接已复制
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you didn't say anything about your target FPGA and the pc you run Quartus. Does this pc have enough memory or is it swaping ? also you didn't mention how you have setup your project.
What Quartus Version do you have ? Maybe the meneu Tools -> Advisors -> Compilation Time Advisors may help youOpen You Quartus Project
Menue Assignments -> Settings Compilation Process Settings choose Parallel compilation . Use all available processors enable Use smart compilation Fitter Settings Set fitter effort to Auto Fit your system should be fast enough a Cyclone II EP2C70 design with ~70% usage is compiled here on a E8500 cpu within 50 minutes. Is your project stored localy or via network ?