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Quartus EDA Netlist Writer

Altera_Forum
Honored Contributor II
‎07-25-2010 01:11 AM
1,491 Views

Hi, 

 

Using Altera Model-Sim to do a gate level simulation. The .vo file that is produced doesn't seem to be modeling the internal RAM's correctly. In the design they are instantiated as 12bit but the EDA netlist has them as 4 bits. 

 

Any help on this?  

 

Regards, 

Rob
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Altera_Forum
Honored Contributor II
‎07-25-2010 08:20 AM
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So far, you're not reporting an error, I think. Internal RAM doesn't offer a 12 Bit mode, depending on the memory size, it may be possibly split into 3x4 bit. If you observe functional errors, you should describe them in detail.

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Altera_Forum
Honored Contributor II
‎07-26-2010 02:03 AM
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I wasn't getting an error. I just noticed that the ram was 4 bits wide. But as you mention, it did instantiate it as three 4-bit memories. 

 

Thank you, 

Rob
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