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Hi guys can someone figure out why Quartus II gives me the following error messages without me assigning anything to the .qsf file:
Error message is below: Error (125048): Error reading Quartus II Settings File C:/altera_trn/VHDL_uppgift_4e/VHDL_uppgift_4e.qsf, line 41 Info (125063): set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME "VHDL_uppgift_4e_vhd_tst " -section_id "VHDL_uppgift_4e_vhd_tst " Error (125022): Section identifier missing or not required Info (125063): set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH "VHDL_uppgift_4e_vhd_tst -section_id eda_simulation" Info (125063): set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH "VHDL_uppgift_4e_vhd_tst " -section_id eda_simulation Error (125022): Section identifier missing or not required Info (125063): set_global_assignment -name EDA_TEST_BENCH_NAME "VHDL_uppgift_4e_vhd_tst -section_id eda_simulation" Info (125063): set_global_assignment -name EDA_TEST_BENCH_NAME "VHDL_uppgift_4e_vhd_tst " -section_id eda_simulation Error (125080): Can't open project -- Quartus II Settings File contains one or more errors Error: Quartus II 64-Bit Hierarchy Elaboration was unsuccessful. 4 errors, 0 warnings Error: Peak virtual memory: 381 megabytes Error: Processing ended: Thu Dec 12 12:47:21 2013 Error: Elapsed time: 00:00:00 Error: Total CPU time (on all processors): 00:00:00 Thanks for any help offered:oops:Link Copied
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Without the qsf file it's a bit hard to determine, but I'm guessing line 41 looks like:
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME "VHDL_uppgift_4e_vhd_tst " -section_id "VHDL_uppgift_4e_vhd_tst " It looks like it doesn't like the -section_id's for these guys. Try changing the lines to: set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME "VHDL_uppgift_4e_vhd_tst " set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH "VHDL_uppgift_4e_vhd_tst " set_global_assignment -name EDA_TEST_BENCH_NAME "VHDL_uppgift_4e_vhd_tst " and see if it helps. Pete- Mark as New
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--- Quote Start --- Without the qsf file it's a bit hard to determine, but I'm guessing line 41 looks like: set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME "VHDL_uppgift_4e_vhd_tst " -section_id "VHDL_uppgift_4e_vhd_tst " It looks like it doesn't like the -section_id's for these guys. Try changing the lines to: set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME "VHDL_uppgift_4e_vhd_tst " set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH "VHDL_uppgift_4e_vhd_tst " set_global_assignment -name EDA_TEST_BENCH_NAME "VHDL_uppgift_4e_vhd_tst " and see if it helps. Pete --- Quote End --- ----------------------------------------------------- Hi Anakha, tried your suggestion but still it did not work. Thanks for the help and time.
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Hi Anakha, here is the qsf file, thanks for the help:
# --------------------------------------------------------------------------# # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # --------------------------------------------------------------------------# # # Quartus II 64-Bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 10:48:14 December 13, 2013 # # --------------------------------------------------------------------------# # # Notes: # # 1) The default values for assignments are stored in the file: # VHDL_uppgift_4ny_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # --------------------------------------------------------------------------# set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name DEVICE EP4CE115F29C7 set_global_assignment -name TOP_LEVEL_ENTITY VHDL_uppgift_4ny set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:48:13 DECEMBER 13, 2013" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation set_global_assignment -name VHDL_FILE VHDL_uppgift_4ny.vhd set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id eda_simulation set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH "VHDL_uppgift_4ny_vhd_tst " -section_id eda_simulation set_global_assignment -name EDA_TEST_BENCH_NAME "VHDL_uppgift_4ny_vhd_tst " -section_id eda_simulation set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id "VHDL_uppgift_4ny_vhd_tst " set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 ms" -section_id "VHDL_uppgift_4ny_vhd_tst " set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME "VHDL_uppgift_4ny_vhd_tst " -section_id "VHDL_uppgift_4ny_vhd_tst " set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/VHDL_uppgift_4ny.vht -section_id "VHDL_uppgift_4ny_vhd_tst " set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top![](/skins/images/045A6C88D0527A93E76B179D7F5E2AFE/responsive_peak/images/icon_anonymous_message.png)
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