Quartus II Assignments -> Pins

[Altera_Forum]

I am new in quartus and altera fpga's. 

I have a Stratix III EP3SL150 and I'm runing quartus II 8.0 web edition and 11.1 web edition as well and in bouth of them I have the same problem.  Wen I load the example that came with the instalation "my first fpga program" to the board it runs ok.   When I folow the tutorial to create my self the program, the first problem is thet when I do Assignments -> device to pick the correct board the model exists bet it saying thar t it is not installed. I use one other board to continue the tutorial, one that the tutorial acepts and everything goes ok, I do processing -> start -> start analysis & elaboration and it is ok with no errors and no warnings. The problen apears when I do assignments -> pins it moves to the correct window has in tutorial but does not apear the I/O pins that I created in the schematic so I cant conect to the output pins of the fpga.  so the main questions are:  Is it possible to download the information for the stratix III EP3SL150 to quartus II? Is it suposed to the free web edition to execute the "my first fpga program" tutorial?

[Altera_Forum]

The web edition of Quartus does not support Stratix devices. Are you running on a development board of some sort?

[Altera_Forum]

Yes, I have Stratix EP3SL150 development boart to use at university and I instaled the altera software that came with it and got the web edition license on altera web page. I can load program to the board and it runs ok but I canot create program´s to it. 

And one other thing I do not find normal is that I tried to create the tutorial for an existing board on quartus just for practice. I used Cyclone III EP3C120C780C7 and stil does not apear the node name of the I/O pins I created on the schematic in order for me to define the conections to the pinouts of the fpga in the "Pin Planer" window.

[Altera_Forum]

First you will not be able to compile a design to work in the Stratix III family using the web edition of the Quartus II tools. You will need to get a full license for the Quartus II tool to compile a design for the Stratix.  

 On your second issue. Did you at least run "Analysis & Elaboration" before you tried to assign I/O pins? If not you need to do so Processing -> Start -> Start Analysis & Elaboration". This is to build the database so that Quartus knows what the hierarchy looks like for your design along with the I/O pins.  Hope that helps  /Boris

[Altera_Forum]

Yes I did thats the previous step of the tutorial.

[Altera_Forum]

Try to compile the design to completion and see if you see the pins then

[Altera_Forum]

Info: Elaborating entity "altpll" for hierarchy "pll:inst1|altpll:altpll_component" 

Info: Elaborated megafunction instantiation "pll:inst1|altpll:altpll_component" Info: Instantiated megafunction "pll:inst1|altpll:altpll_component" with the following parameter:  Info: Parameter "bandwidth_type" = "AUTO"  Info: Parameter "clk0_divide_by" = "10"  Info: Parameter "clk0_duty_cycle" = "50"  Info: Parameter "clk0_multiply_by" = "1"  Info: Parameter "clk0_phase_shift" = "0"  Info: Parameter "compensate_clock" = "CLK0"  Info: Parameter "inclk0_input_frequency" = "20000"  Info: Parameter "intended_device_family" = "Cyclone III"  Info: Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll"  Info: Parameter "lpm_type" = "altpll"  Info: Parameter "operation_mode" = "NORMAL"  Info: Parameter "pll_type" = "Fast"  Info: Parameter "port_activeclock" = "PORT_UNUSED"  Info: Parameter "port_areset" = "PORT_UNUSED"  Info: Parameter "port_clkbad0" = "PORT_UNUSED"  Info: Parameter "port_clkbad1" = "PORT_UNUSED"  Info: Parameter "port_clkloss" = "PORT_UNUSED"  Info: Parameter "port_clkswitch" = "PORT_UNUSED"  Info: Parameter "port_configupdate" = "PORT_UNUSED"  Info: Parameter "port_fbin" = "PORT_UNUSED"  Info: Parameter "port_inclk0" = "PORT_USED"  Info: Parameter "port_inclk1" = "PORT_UNUSED"  Info: Parameter "port_locked" = "PORT_UNUSED"  Info: Parameter "port_pfdena" = "PORT_UNUSED"  Info: Parameter "port_phasecounterselect" = "PORT_UNUSED"  Info: Parameter "port_phasedone" = "PORT_UNUSED"  Info: Parameter "port_phasestep" = "PORT_UNUSED"  Info: Parameter "port_phaseupdown" = "PORT_UNUSED"  Info: Parameter "port_pllena" = "PORT_UNUSED"  Info: Parameter "port_scanaclr" = "PORT_UNUSED"  Info: Parameter "port_scanclk" = "PORT_UNUSED"  Info: Parameter "port_scanclkena" = "PORT_UNUSED"  Info: Parameter "port_scandata" = "PORT_UNUSED"  Info: Parameter "port_scandataout" = "PORT_UNUSED"  Info: Parameter "port_scandone" = "PORT_UNUSED"  Info: Parameter "port_scanread" = "PORT_UNUSED"  Info: Parameter "port_scanwrite" = "PORT_UNUSED"  Info: Parameter "port_clk0" = "PORT_USED"  Info: Parameter "port_clk1" = "PORT_UNUSED"  Info: Parameter "port_clk2" = "PORT_UNUSED"  Info: Parameter "port_clk3" = "PORT_UNUSED"  Info: Parameter "port_clk4" = "PORT_UNUSED"  Info: Parameter "port_clk5" = "PORT_UNUSED"  Info: Parameter "port_clkena0" = "PORT_UNUSED"  Info: Parameter "port_clkena1" = "PORT_UNUSED"  Info: Parameter "port_clkena2" = "PORT_UNUSED"  Info: Parameter "port_clkena3" = "PORT_UNUSED"  Info: Parameter "port_clkena4" = "PORT_UNUSED"  Info: Parameter "port_clkena5" = "PORT_UNUSED"  Info: Parameter "port_extclk0" = "PORT_UNUSED"  Info: Parameter "port_extclk1" = "PORT_UNUSED"  Info: Parameter "port_extclk2" = "PORT_UNUSED"  Info: Parameter "port_extclk3" = "PORT_UNUSED"  Info: Parameter "width_clock" = "5" Info: Found 1 design units, including 1 entities, in source file db/pll_altpll.v  Info: Found entity 1: pll_altpll Info: Elaborating entity "pll_altpll" for hierarchy "pll:inst1|altpll:altpll_component|pll_altpll:auto_generated" Info: Quartus II Analysis & Elaboration was successful. 0 errors, 0 warnings  Info: Peak virtual memory: 191 megabytes  Info: Processing ended: Wed Feb 29 19:25:29 2012  Info: Elapsed time: 00:00:05  Info: Total CPU time (on all processors): 00:00:02

[Altera_Forum]

Brilliant. I did has you told me. I did "start compilation" and then I did Assignments -> Pins and finally the node names and direction appeared correctly on the pin planer window. 

 Thank you very mush for your help.

[Altera_Forum]

Great good luck with your project.