Quartus II Initalization Problem...

[Altera_Forum]

In the code below, the num variable is initialized to 0. It basically gives an error saying it is stuck in the while loop. When I explicity state that num is 0 inside begin of the process, it works, but that would cause problems in the coding. Any suggestions? Thanks.  

   library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all;   entity t_input is   port(  EN : in STD_LOGIC  ); end t_input;   architecture t_input of t_input is begin   process (EN)   variable num: INTEGER := 0;   begin     while ( num < 5 ) loop  num := num + 1;   end loop;    end process;  end t_input;

[Altera_Forum]

Not to avoid the original questions, but what is it you're trying to do? Do you want num to be something in the actual design(a value to be used), or is this just a test and you use it as a conditional or variable somewhere else? 

If you're using it as something "physical" in the design, you're going to need a clock to store it's values and have safe additions. I would also recommend making it a signal rather than a variable(I personally recommend using signals almost all the time, and use variables only when they truly provide something a signal can't do...)

[Altera_Forum]

To understand, why the compiler sees an endless loop here, you must consider what a for or while loop means in synthesizable code. It is basically a method to generate parallel logic, one instance for each iteration. This can only be done, if the number of iterations is finite. Quartus sets an arbitrary limit of 10000 iterations to break a possibly infinite iteration. In the present case, the iteration is effectively a NOP, cause nothing depends on the loop variable, but the limit is evaluated anyway. 

 When checking the range covered by the loop variable, Quartus apparently doesn't see, that it would have an effective upper limit. Probably the variable storage between two process cycles isn't included in the range evaluation. Regarding useful applications of a while loop, this isn't a problem, I think. If you intend a construct, where the range of an iteration is modified depending on another condition, you can use a for loop that spans the range and an if condition, thats selects the values to be used in processing.

[Altera_Forum]

Maybe you can also just add a range to the integer declaration, this would tell quartus which values it can expect. It is always a good idea to constrain integers that way in a design if you want to use it in hardware. 

 variable num: INTEGER range 0 to 5 := 0;   Lokla

[Altera_Forum]

Also a range in variable definition doesn't help here. I wonder, if the variable definition is used at all when evaluating the loop range. Personally, I always use FOR LOOPS in VHDL iterations, they have a clearly defined range and give less room for misunderstandings.  

 By the way, most infinite loops in accidental VHDL code I've seen have been due to misunderstanding the VHDL iteration concept as means to achieve a C-like sequential program flow.