problem with synthesise or crossing clock domains ???

[Altera_Forum]

Hello everybody, 

 I'm not quite sure where to post my problem, because I don't actually know what the problem might be.  I'm using a CycloneIII. My design has an IP-Softcore that we bought from another firm. This code is encrypted vhdl / netlist and consists of a 15bit data bus and 8 bit address bus.  My job is to interface the parallel bus and apply data and address through a serial interface. The ip-core runs on a 64Mhz clock. The serial clock is generated with 40Mhz clock and constists of three cycles: clk = '0', data out, clk = '1'. So the clock speed is about 13MHz with 33% duty cycle. I wrote a statemachine with a shift register, that receives a stream of data: first one bit for read access, one bit for write access, 8 bits address and 16 bit data. The shift register / statemachine is triggered on the rising edge of external SPI clock. Data and address are always applied to the bus when received. One cycle later (75ns) the requiered strobe signals (rd/wr and cs) are held low for at least 100ns. (So I am sure the address and data bits have settled before i start a strobe command.) In this period, the ip core pulls low a ready-signal, so I can be sure the data was read. I don't check the ready signal. but the acknowledge comes within 50..70ns. This is what i simulated and what i measured with a logic analyser. In my opinion i did everything i have to to synchronise the two domains.  To make a long story short: The problem is that this works only about 98%of time. I use my code for three components, so everything should be equal. Depending on my settings for synthesise and place&route i get very different results. the best one is two components working 100%, one at 98%, but normaly i get problems on all 3 components. I use a testing register within the IP to write a word of data and read it back directly. When I cycle through from 0 to FFFF i get between 400 and 1000 wrong values that I read back. If I read a wrong value again, the same value is reported. So reading is not my problem. (I also checked the serial bus with the logic analyser. there is really wrong data on the bus; I also read a hardcoded ID string from the core correctly) I am not sure, if this is only a problem on synthesis, or if i got serious problems with synchronising.  I am open for any suggestion, because it is really starting to annoy me. Thanks for any feedback Oliver

[Altera_Forum]

Make sure the design is fully constrained for timing. In the Classic Timing Analyzer, run "Processing --> Start --> Start Classic Timing Analyzer Constraint Check". In TimeQuest, run "Report Unconstrained Paths" (report_ucp) and "Check Timing" (check_timing). You might need recovery/removal analysis on some asynchronous paths like reset. TimeQuest runs this analysis by default. In the "More Timing Settings" dialog box for the Classic Timing Analyzer, turn on "Enable Recovery/Removal Analysis". 

 The Design Assistant might find something asynchronous that you didn't intend or a problem with your cross-domain paths. Run "Processing --> Start --> Start Design Assistant".