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All,
For further investigation in my current design i would like to use the signaltap II logic analyser. After creating and enabling a signaltab file (At first only 1Clock and 3 Nodes) with the SignalTab II Editor the stp1.stp file was added to the design but unfortunately the design can't be compiled anymore. During Analysis&Synthesis the following Error appears: Quartus II Internal Error *** Fatal Error: Access Violation at 0X009C4DF4 Module: quartus_map.exe Stack Trace: 0x4DF4 : QTL_ZOFSTREAM::close + 0x34 (ccl_qtl) 0x55F25 : sgn_qic_helper + 0x4A2D5 (synth_sgn) End-trace HELP!!! Dieter Quartus II Software Version 9.0Link Copied
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Such things happen. You should send a service request to Altera support. You can try to rebuild the design by deleting the db directory and, if the error persists, build a new Signal Tap file, possibly with slightly different signal nodes. The error may also be triggered by irregular properties of your design.
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Hello!
I've found the problem. Working on the project over LAN caused the error. I had to copy the complete project on local pc. Dieter- Mark as New
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--- Quote Start --- I had to copy the complete project on local pc. --- Quote End --- Apart from other possible problems, it's strongly recommended for performance reasons You easily get several millions of individual file accesses during a compilation run.

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