Quartus II: Reading back programmed file from chip?

[Altera_Forum]

I have lost the original design for a project and at least need to read back the data programmed into my EPCS1SI8 part and save it. 

Is this possible and what option do I select in Quartus II?

[Altera_Forum]

Hi, 

 I never tried, but the "examine" feature of the Quartus programmer should be able to do that: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd08192010_758.html (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd08192010_758.html).  There also seems to be another thread about this topic: http://www.alteraforum.com/forum/showthread.php?t=42587 (http://www.alteraforum.com/forum/showthread.php?t=42587)  However, this will of course only give you back the data stream, no source files (VHDL/Verilog).   Best regards, GooGooCluster

[Altera_Forum]

Thanks, I'll give that a shot tomorrow. Yeah, I would like to recover the source but right now I need to get another board up and running, so if I can capture the data and save it that will be a good start. 

 That link you provided mentioned that the data would have to be captured/saved as a .jic file instead of the original .pof Not familiar with the .jic      --- Quote Start ---  Hi,  I never tried, but the "examine" feature of the Quartus programmer should be able to do that: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd08192010_758.html.  There also seems to be another thread about this topic: http://www.alteraforum.com/forum/showthread.php?t=42587  However, this will of course only give you back the data stream, no source files (VHDL/Verilog).   Best regards, GooGooCluster  --- Quote End ---  

[Altera_Forum]

Thanks for your help. 

 I was able to use the "examine" feature and recover the POF file.

[Altera_Forum]

--- Quote Start ---  Hi,  I never tried, but the "examine" feature of the Quartus programmer should be able to do that: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd08192010_758.html (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd08192010_758.html).  There also seems to be another thread about this topic: http://www.alteraforum.com/forum/showthread.php?t=42587 (http://www.alteraforum.com/forum/showthread.php?t=42587)  However, this will of course only give you back the data stream, no source files (VHDL/Verilog).   Best regards, GooGooCluster  --- Quote End ---    Thanks for sharing this. It is useful.

[Altera_Forum]

Great info on the "examine" feature. Thanks.

[CLope32]

Hello all,

I have tried to extract the program from a CPLD, but i can't see the examine feature in the programmer. Where is it?