Quartus II Timing simulation

[Altera_Forum]

Hi all, 

 For my VHDL design, I tried to simulate it with some conditions.  By fundamental, how far this simulation results would be matched with real time testing results ?  Is there any parameters which distinguish this tool simulation results and real time testing results?   Regards, Vijay

[Altera_Forum]

There are two types of simulation, functional and timing. Functional is always useful since it finds functional issues with your code. I assume you're talking about timing sims. 

The timing sims use fixed numbers, i.e. fixed delay values that are generally either worst case(slow corner) or best case(fast corner) numbers. The default is slow numbers. In general timing sims are slow and I don't feel like they reveal a whole lot. Most designers I see do functional sims and static timing analysis(you should always do static timing analysis), which is done via TimeQuest. Basically STA defines relationships between clocksn that data will pass thru. For example, a 100MHz clock will have a default 10ns setup requirement and 0ns hold requirement. That means data transfering between these edges must be longer than 0ns and less than 10ns(clock skew gets accounted for too). If you pass STA, which covers all timing models, then a timing simulation would have the data pass between clock edges, just like a functional simulation would.   Where it gets tricky is asynchronous design, which you want to avoid as much as possible. STA can't properly evaluate an asynchronous design since you don't have clear pass/fail delay criteria. Timing simulations give a better idea of what might happen(i.e. they can show something you hadn't planned on), but they're not going to model the hardware exactly. For example, a data bus might take 8ns in the slow model to go between two registers. But in hardware some of the bits might be much faster, and probably none of them will be as bad as 8ns, except under extreme conditions. Timing simulation was used more by ASIC designers because the cost of having an error was so high that it was worth the effort.   Of course, this is a topic that people have different views on. If you give more info on what you're trying, you might get a better response.  (Oh, and to answer more of the question, if a slow model simulation shows data coming out at time 15ns, and a fast model simulation shows it coming out at time 8ns, then your hardware will show it coming out somewhere between there. Different die, different conditions will vary those results within that range.)