Good afternoon,
I have a question in relation to Quartus-II web edition and Nios II/e licence restrictions.
I am considering starting an open community project using the Terrasic DE0-NANO that I have recently purchased and I would like to understand any licencing issues at the outset. I am very new to FPGA but I am running through the Altera online academy and hope to successfully complete the project well within the free licence terms.
The 10,000 line code limit covers the VHDL within Quartus II but does this also apply to the C/C++ codelines loaded within the NIOS IDE and together they sum total towards the line limit or is it just the NIOS-II and FPGA VHDL that contribute to the limit and the C/C++ is excluded and is just limited by the available SDRAM on the dev board ?
If the above is true, how many typical codelines are consumed by the NIOS-II/e so I can gauge the remaining capacity ?
As you can understand that as the project costs need to be kept low to keep momentum going, I am trying to avoid future pitfalls and licence costs.
Many thanks for your help.
Andy
