Hi everybody,I'm trying to use the ddr2 controller ALTMEMPHY on my Cyclone III ep3c120f780 devboard in QSYS. I generate my sopc and then compile my quartus project with the FPGA top file declared in VHDL. Then I have an error at the end of the synthetis (97%) : Error (15873): Output port DATAOUT of DDIO_OUT primitive "MySOPC_cyIII_devboard:MyFPGA_cycloneIII_inst|MySOPC_cyIII_devboard_altmemddr:altmemddr|MySOPC_cyIII_devboard_altmemddr_controller_phy:MySOPC_cyIII_devboard_altmemddr_controller_phy_inst|MySOPC_cyIII_devboard_altmemddr_phy:MySOPC_cyIII_devboard_altmemddr_phy_inst|MySOPC_cyIII_devboard_altmemddr_phy_alt_mem_phy:MySOPC_cyIII_devboard_altmemddr_phy_alt_mem_phy_inst|MySOPC_cyIII_devboard_altmemddr_phy_alt_mem_phy_clk_reset:clk|altddio_bidir:DDR_CLK_OUT.ddr_clk_out_p|ddio_bidir_e4h:auto_generated|ddio_outa" must drive input port I of an I/O OBUF primitive It comes from the alt_mem_phy_clk_reset of the altmemddr_controller but this instance is generated automatically and I don't understand where is the error in my code. I have also declared the FPGA top in verilog an then the error disapear when compiled. Can somone help me because I want to program it in VHDL. I have also attached my FPGA top files verilog and VHDL. The SOPC is based on the design_standard of the ALTERA devboard.
I found the error. Some ports are declared in the qsys example as std_logic_vector(0 donwto 0) you need to define them as std_logic especially for mem_clk of the altmemddr.
--- Quote Start --- I found the error. Some ports are declared in the qsys example as std_logic_vector(0 donwto 0) you need to define them as std_logic especially for mem_clk of the altmemddr. --- Quote End --- Thanks kakaboud! Your answer fixed the problem for me - DDR2 in a QSYS system with vhdl as top level. I had to change the top level pin and the QSYS component declaration to std_logic instead of std_logic_vector(0 downto 0). Cheers, Greg