Quartus II negative bus dimensions in Schematic file

Altera_Forum · ‎05-08-2009

I want to use the fixed point package provided here: http://www.accellera.org/apps/group_public/documents.php?wg_abbrev=vhdl

I can compile the library and use the files, but a problem arises when I create a schematic file and try to synthesize. To use the fixed point numbers I have to declare the bus width like so: var_name sfixed (1 downto -30)

When I create a block out the file and try to synthesize it, I get an error about illegal bus width "-30". Is there a way to get around this? Or I cannot use negative numbers as a bus width?

Thanks

Altera_Forum · ‎05-08-2009

The schematic editor has alot of limitation whan it comes to creating blocks from HDL code. For eg. you cannot have generics that are more complicated than boolean or integer, and at one time the schematic editor would not make schematic blocks for 2d arrays in VHDL, but it would for AHDL. :confused:

Anyway, the best thing to do is forget about using the schematic editor and do it all in VHDL.

Altera_Forum · ‎05-08-2009

I would rather do most of my work in VHDL, but sometimes don't you need to use Quartus for specific things like PIN assignments? The only way I know to assign PINS to a board is by using a CSV file and map the pins placed on the Schematic file, is there a VHDL way of doing this? And for simulation, don't I need to get the input pins from the schematic file also? How would I simulate this my example if I can't placed it in the schematic file?

Thanks for your reply!

Altera_Forum · ‎05-08-2009

you dont need schematics at all.

Just create a top level VHDL file that instatiates the sub-blocks and has a port declaration that would connect to pins on the device, and then go to Assignments -> Assignments editor and assign each of the top level IO's in the VHDL file to a pin. The top level IOs normally have to be std_logic or std_logic_vector.

As for simulation: what you normally do is create a VHDL Testbench, that controls all the IO to the block and clock generation. The testbench doesnt need to be synthesisable, so to generate a clock you can do something like:


  signal clk : std_logic := '0';
  signal reset : std_logic;
begin 
  reset <= '1', '0' after 50 ns;
  clk <= not clk after 10 ns;

and do all stimulus from the testbench. Normally you'd run something like this in modelsim.

Altera_Forum · ‎05-08-2009

Thanks so much, I was a little confused on how to do this in Quartus because I learned it one way, and I thought that was THE way, I guess not!

As for simulation, why the heck bother with Quartus' simulator tool if you want to do something a little bit more "complex". I thought it would be easier than making VHDL testbenches which can become tedious to write after a while. Now time to review my ModelSiml stuff :rolleyes: