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Quartus IP SDC files

SKon1
Novice
2,990 Views

Hello,

 

I'm using a Native PHY Transceiver in my Arria V design.

The IP is generated successfully - but I can't see any SDC files generated with it...do I have to write the timing constraints for it myself ?

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Abe
Valued Contributor II
840 Views

Hi,

 

When generating the PHY, click the EDA Options button and select the Generate Netlist option. Now, generate the PHY IP again. This time you will find the SDC generated.

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KhaiChein_Y_Intel
840 Views

You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/xcvr_user_guide.pdf (SDC Timing Constraints for Arria V Transceiver Native PHY IP Core )

 

SKon1
Novice
840 Views

Abe,

I checked the generate netlist box and regenerated the PHY - can't see any .SDC in the folder

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SKon1
Novice
840 Views

KYeoh,

 

I see the SDC section for the Arria V.

Can't find any "set_output_delay" constraints for the data output.

It's basically only false paths...am I missing something ?

 

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KhaiChein_Y_Intel
840 Views

Hi Skon1,

 

The constraint for set_output_delay is not needed.

SKon1
Novice
840 Views

Did you see the document ?

I could see only false_path constrains in it...is that all that's required ?

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KhaiChein_Y_Intel
840 Views

Yes. You just need to create clock and set false path to those asynchronous path.

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