Quartus , Platform Designer, TSE IP

[awaissman]

Hello,

I have quarus 24.1 version and trying design Ethernet SGMII interface.

I am trying use TSE IP.

First i like generate example design , but keep getting error bellow.

Is there way generate example design?

Thanks,

Error: eth_tse_0: Example Design is available only for the 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS/2XTBI PCS core variation with Use internal FIFO and Align packet headers to 32-bit
boundary options disabled.

[paveetirrasrie_Intel]

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.

Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Your case will be attended by AE soonest possible.

Thank you again for your patience and understanding, and we are committed to provide you with the best possible support.

[paveetirrasrie_Intel]

Hi,

Based on the error, looks like some IP configuration error.

Kindly follow the steps mentioned in User Guide to generate the example design and let me know if you faced similar error.

https://www.intel.com/content/www/us/en/docs/programmable/683402/22-4-21-1-0/design-walkthrough.html

Regards,

pavee

[awaissman]

Hi Pavee,

Thanks for the reply.

Problem when I create TSE IP in the configuration window under "Example Design" I do not see any Example available for any Core configuration.

I am using the Cyclone 10 GX FPGA.

Albert,

[paveetirrasrie_Intel]

Hi,

Apologies for the delayed response. Kindly allow me 1 day to check on this and will contact you back soon.

Regards,

Pavee

[paveetirrasrie_Intel]

Hi,

Good day.

Below link is for TSE design. Kindly let me know if this works for you.

https://www.intel.com/content/www/us/en/design-example/714768/intel-cyclone-10-lp-fpga-intel-fpga-triple-speed-ethernet-and-intel-onboard-phy-chip-reference-design.html