Quartus error while compiling a reference design

Altera_Forum · ‎04-27-2011

When compiling the reference design "Interfacing a 267-MHz DDR2 SDRAM with an Arria II GX FPGA" with Quartus 10.1sp1 on CentOS 4.6, I get the following error message. It says the error is in a tcl file coming with the Quartus suite. What can I do for it? Thanks!

Error: Tcl error: ERROR: Compilation database is newer than the last call to "create_timing_netlist". Use the "delete_timing_netlist" Tcl command before using "load_report".

while executing

"load_report"

invoked from within

"if [is_project_open] {

if {$options(qsf2sdc)} {

post_message -type info "Migrating assignments from quartus_tan"

set value [get_ini_var -nam..."

(procedure "main" line 121)

invoked from within

"main"

(file "/app2/altera/10.1/quartus/common/tcl/internal/qsta_default_script.tcl" line 1104)

Altera_Forum · ‎04-27-2011

Is your reference design from V10.1sp1? or from an older release?. Can you post the messages that TimeQuest (quartus_sta) displayed before the error?

Altera_Forum · ‎04-27-2011

Thank you for your reply.

The reference design is downloaded from the Altera website.

It is for 9.1 but I've already re-generated the IPs using 10.1sp1.

Altera_Forum · ‎04-28-2011

Hi,

My guess is that the reference design has QSF timing assignments (for the Classic Timing Analyzer), and the V10.1sp1 TimeQuest is having trouble trying to convert them to an SDC file.

I would recommend one of the following three options:

1.- Remove the Timing assignments from the QSF and manually create an SDC file for TimeQuest

2.- Use V9.1 to compile and run quartus_sta --qsf2sdc to generate the SDC file. Then remove the timing assignments from the QSF, and try again with V10.1sp1 (and using the generated SDC file).

3.- Just try to use the V10.1sp1 reference design. Any reason why you are using the V9.1 one?