Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
14943 Discussions

Quartus help - RTL Viewer does't update after changes in the code

Altera_Forum
Honored Contributor I
1,337 Views

Hello, 

 

On the very first time i open the RTL Viewer in any new project - it generates a schematic. 

But if i change something in the Verilog code, compile, and open the RTL Viewer again, the RTL Viewer doesn't update accordingly. 

 

The only way i can get it to update is clicking: 

project > clean project 

and then open the RTL Viewer again. 

 

is there a nicer, more direct way to do it? 

 

thx
0 Kudos
6 Replies
Altera_Forum
Honored Contributor I
97 Views

What kind of changes are you making to the design? Are you saying you do a full recompile and RTL Viewer doesn't reflect those changes? What is your indication that things haven't changed? 

 

If you make small changes to a design, you might not notice what synthesis has changed.
Altera_Forum
Honored Contributor I
97 Views

When you say you recompile after editing the code, are you doing a full recompile or just analysis and elaboration? 

 

Also, what version of the software are you using? And are you using incremental compilation? Are there any strange warnings appearing during compilation? 

 

Something is clearly stuck in the compilation database and either it's a problem with your installation or perhaps you've set up something with incremental compilation that is preventing the design from being recompiled.  

 

What does the technology map viewer look like when you change the code?
Altera_Forum
Honored Contributor I
97 Views

I think i'm doing a full recompile: just pressing this purple "play" button: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=15492  

 

at the end of the compilation i get this: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=15493  

 

i get only those warnings: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=15494  

 

this is my version: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=15495  

 

later i also tried to start and compile only analysis and elaboration, doesn't work also.. 

what is incremental compilation? and if i'm using it by a mistake, it should detect my changes, no? 

 

 

the technology map viewer (post-mapping), before and after the recompile: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=15496
Altera_Forum
Honored Contributor I
97 Views

Go to Assignments -> Design Partitions Window. Make sure the Netlist type is set to Source so it will always recompile back from source code.

Altera_Forum
Honored Contributor I
97 Views

it is already on source... 

 

https://alteraforum.com/forum/attachment.php?attachmentid=15497&stc=1  

 

should it be "Top" there? or something else..? 

 

is there a way to only force generating a new netlist? 

(though it is a "bandage" it will be 1 step forward)
Altera_Forum
Honored Contributor I
97 Views

I'm not sure what's going on then. Does this happen even if you create a brand new project? Can you try using a newer version of the software (13.1 is now almost 5 years old)?

Reply