Quartus synthesis'result and RTL function are mismatch

[Altera_Forum]

Hi,All 

  I using one design using system verilog and compile this design on Quartus 12.1  And I got the gate level netlist which functionality are not the same with RTL. And then I do some debug and got the reason caused mismatch result.  It seems synthesis tool's bug.   Attaching file contain the test case I do. It contain two folder.  match folder contain the design that RTL/gate-level have same functionality.  mismatch folder contain the design that RTL/gate-level haven't same functionality.

[Altera_Forum]

If there's a synthesis bug, I would file a Service Request. I would also be very clear in showing snapshots from gate-level simulation and RTL simulation and what is different, as well as testbenches to run the simulations. Right now it's just the .sv files, which nobody would know how to simulate, let alone where to look for mismatches.

[Altera_Forum]

HI, 

Because this .sv is come from part of my design,it will take some time if you still need testbech.   But if you check the the synthesis result in mismatch folder using "Technology Map viewr" and check the output pin " fifoOut_dat", you will found those pin was assign to zero.  If you check the the synthesis result in match folder using "Technology Map viewr" and check the output pin " fifoOut_dat", you will found those pin was assign to part of design.  Ya-Chau          --- Quote Start ---  If there's a synthesis bug, I would file a Service Request. I would also be very clear in showing snapshots from gate-level simulation and RTL simulation and what is different, as well as testbenches to run the simulations. Right now it's just the .sv files, which nobody would know how to simulate, let alone where to look for mismatches.  --- Quote End ---  

[Altera_Forum]

I compiled in Q13.0 and in the both cases see registers driving that output, so if you're using an older version, it appears to be fixed.

[Altera_Forum]

OK, Thank you. I will try to update to Q13.0

[Altera_Forum]

Hi,  

  I and my colleague find another RTL/synthesis's mismatch and we still use Q12.1 , but maybe you have interest to check it out.  Attaching file contain test bench(stim.sv) and test case(testCase.sv) we make.  Ya-Chau

[Altera_Forum]

Hi, 

After I try the Q13.0 sp1, the mismatch in testCase.tar.gz didn't go away. I wonder if you still need test bench to figure out the problem. If yes, I will spent some time try to do tb bench when I have free time.