Quartus2 - altpll megawizard plugin - no clock output in simulation waveform editor

[Altera_Forum]

Hi, 

 in my schematic entry I use the altpll block to divide my clock.  I`ve routet the outputs to GPIO pins and could measure them via oscilloscope. But when I use them for simulation in the waveform editor, there is just a low signal at the outputs. So, check out my screenshot, to see that the allclear button works, and the pll is going to start, after alclr is low. So it seems, that the pll works, and as I told you, I can measure the clock signals via oscilloscope at the gpio pins.  So, what did I wrong?  I would be happy, if someone could help me.  best regards sektor

[Altera_Forum]

The PLL needs time to lock to the input clock. Try running your simulation longer (10ms ?) Try adding the 'locked' output of the PLL as a diagnostic aid.

[Altera_Forum]

Thank you, that might be the solution, I didn`t think about tht the pll isn`t locked yet. So thank you. 

But in the waveform simulation tool, i only can set the maximum simulation time to 100us.  Is there a workaround, to capture the pll signals into the waveform editor?

[Altera_Forum]

Try using Modelsim. It doesn't have any such limitation.

[Altera_Forum]

Thank you for your answer. 

Yes, I tried. But I´m not experienced in ModelSim. so I tried the example from the User Guide. This works pretty. But I cannot implement my current project into ModelSim, because there are to many different signals and files, so I didn`t get it to work. Therefore I used the Waveform Editor.  I`m sure, it is not so difficult, to simulate it via ModelSim, but I need a short introduction. So perhaps someone could assist me to getting started?  When I open the directory "work" there are only the entities, but there are no I/O ports or something else to select and generate a waveform. In the msgs window, there is "No Data". Sorry about those silly questions, but I`m totally new in ModelSim, so how can we make this thing working?  I also used Simulink to create some designs. It`s possible to start ModelSim out of Simulink, so the "wave"-window in ModelSim is automatically configured with the necessary signals. It is possible to have a solution like that out of quartus??  Hope to get some help, thanks a lot in advance.  kind regards

[Altera_Forum]

If you look around, you will find some tutorials (like this one, which is older but still relevant: http://www.altera.com/literature/ug/ug_gs_msa_qii.pdf)  

 But getting started is quite easy by letting Quartus do much of the work for you:  1) get your project completed to the point that Quartus is able to compile it.  2) if you haven't already, create a testbench HDL file. At a minimum, just have it generate a clock and reset for your system.  3) in Quartus, go to Assignments->Settings.... -> EDA Tool Settings -> Simulation and review the other settings, but go down to the NativeLink section and click on "Compile test bench" and then define your test bench (give it a name, tell it where your testbench HDL file is). This is shown on page 5 of the PDF mentioned above.  4) execute a Quartus compile. During this process, Quartus will write a Modelsim .do TCL script to command Modelsim how to compile your source and simulate it with your testbench.  5) after the compilation completes, click on Tools->Run Simulation Tool-> RTL Simulation.. Quartus will launch Modelsim and have it run the .do script that it just wrote for you. It will compile your HDL files, load your testbench top level into the simulator, add the testbench signals to the wave window, and start it executing.   There's much more you can do beyond this, but hopefully this can get you started.

[Altera_Forum]

Hey Ted, 

thanks a lot for your answer!!  generally:  Before i changed to quartus, I used simulink, i also got signal generators in my simulink design and after compiling, the signals were shown in the waveform window. Now, i use quartus and got no singal generators in my schematic, therefore, I used the waveformeditor to create my input signals, clock and so on manually.  How does this thing work in ModelSim? Are there stimuli, you can choose from?   according to your answer:  The tutorial you linked, was exactly the one I used to.  But there is a difference according your post:    --- Quote Start ---  3) in Quartus, go to Assignments->Settings.... -> EDA Tool Settings -> Simulation and review the other settings, but go down to the NativeLink section and click on "Compile test bench" and then define your test bench (give it a name, tell it where your testbench HDL file is). This is shown on page 5 of the PDF mentioned above.  --- Quote End ---    So, the tutorial says, select "none" under "NativeLink settings".  You told me to use "compile tesbench". so, when i do this, i have to create a new one (see the screenshot below). But i´m not sure, which simulation file i should choose.  In summary, when i follow the tutorial, there is no project and there are no waveforms in ModelSim.  So perhaps the point to get it working is, to do the thing in 3) correctly as you told?!?  Thanks a lot in advance.

[Altera_Forum]

--- Quote Start ---   So, the tutorial says, select "none" under "NativeLink settings".    --- Quote End ---    Sorry, I only skimmed the article and saw the screenshot had "Compile test bench:" checked and filled in. This is actually what you want to do (i.e. don't say "None"). Just create a simple test bench in HDL and fill out that dialog box.  When you do this, Quartus will generate a more substantial .do script which will compile your files and load the simulation, and add some top level signals to the wave. If you leave it at "None", you get the default behavior which you are currently observing, which isn't that useful when you're first getting started like this. It compiles your modules to the work library, but doesn't load your top level simulation.

[Altera_Forum]

Hey Ted, 

thank you for the reply.  It simply doesn`t work using the description. My steps:  1. Check if the design is compileable. 2. File -> Create/Update -> Create HDL Design File from current design --> so i receive a .v File.  After that, i follow the steps we already discussed and use the .v file as "test bench file".  Running RTL Simulation, ModelSim opens but no wave files or something else in the project.

[Altera_Forum]

Attached is a simple counter + PLL project. The file 'counter.v' was written by hand, while 'simulation/modelsim/counter.vt' was generated by Procession->Start->Start Test Bench Template Writer. 

I then added the test bench clk, reset generation to the template.  Open the project, compile it, and then launch the RTL simulation. Modelsim should run for 100ns and the wave window should have all of the testbench (top level) signals.  This is just an illustration of getting the basics working.   Back in your project you are working on, you probably just need to run the "Start Test Bench Template Writer", modify it to add clk/reset generation, and then define the test bench in the Settings dialog box.    If you are still stuck, post a .qar of your project ( or a dummy/simplified project if you can't share your full project ).

[Altera_Forum]

Hello Ted, 

thanks a lot again for your support.  Sorry for my questions, but for a newbie its hard to get started.  Your design worked well and in the meantime, I recognized, that I didnt`t see the "Transcriptor" Window in Modelsim. But now, i got more information.  Modelsim stopped the simulation with an error, because a file called "../../rtl_work.filename" could not be found. The file isn`t in the directory, so how to create this file?   And let me ask you, what exactly do you mean with "modify it to add clk/reset generation".  Is it to add a clock and a reset from the IP catalog?   For your information, actually i receive the clock from an external signal, so i just got an input port. In the waveform editor, you could generate a clock. Is it possible to work like that in Modelsim to or is it necessary to use the IP blocks as mentioned in my question above?  Thank you in advance.

[Altera_Forum]

--- Quote Start ---   Modelsim stopped the simulation with an error, because a file called "../../rtl_work.filename" could not be found. The file isn`t in the directory, so how to create this file?    --- Quote End ---    I'm not sure what that file is or how you would create it. If you post your project, someone may take a look.    --- Quote Start ---   And let me ask you, what exactly do you mean with "modify it to add clk/reset generation".  Is it to add a clock and a reset from the IP catalog?    --- Quote End ---    Open the counter.vt file and search for 'clk' and 'reset_n' and you will see where I added my clk/reset generation. You need to do the same/similar in your own test bench file.    --- Quote Start ---   For your information, actually i receive the clock from an external signal, so i just got an input port. In the waveform editor, you could generate a clock. Is it possible to work like that in Modelsim to or is it necessary to use the IP blocks as mentioned in my question above?   --- Quote End ---    The tutorial PDF tells you how to do it in Modelsim. My project and my suggestion is to do it in (Verilog) HDL in your test bench file. It's pretty simple, and yes almost all projects get set up like this.