Query related to I2C slave IP and SDM IP

[sneha_wagh]

Hi,

I have attached the document that seeks the information related to I2C slave component and SDM IP component integration. 

Can you help us to resolve the requested queries ?

Regards.

[JingyangTeh_Altera]

Hi Sneha

You could try out using SignalTap to probe the QSPI signals.

https://www.intel.com/content/www/us/en/docs/programmable/683819/21-3/logic-analyzer-introduction.html

Regards

Jingyang, Teh

[sneha_wagh]

Ok, 

After going through the document, can you confirm below flow ?

VCS simulator pattern generator for mailbox on avalon interface -> mailbox client IP receiving the avalon signals -> SDM IP -> SDI QSPI IO pins tapped in Signal Tap Debugger -> VCS simulator analyzing the Signal Tap captured data.

Also can we use this QSPI interface i.e. AVS pins of the Flash after configuration ? Or is this interface is only meant to access the flash for configuration purpose ?

Regards

Sneha

[JingyangTeh_Altera]

Hi Sneha

Yeah the flow is correct.

For the SDM QSPI flash access is mainly for configuration purpose only.

Regards

Jingyang, Teh

[sneha_wagh]

Thanks Jingyang,

We would like to use the QSPI flash via SDM port for the general flash access also after the configuration process by our inhouse custom processor that will be part of FPGA design. Hope this is not the problem, as different Intel documents support this use case.

Regards

Sneha

[JingyangTeh_Altera]

Hi Sneha

I do not see a problem why it could not be done.

Could you share me the document that you are referring that mention this could not be done?

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

Any update on this case?

Regards

Jingyang, Teh

[sneha_wagh]

Hi Jingyang,

Don't know why my last update did not get posted here. I was trying to say that most of the documents mentioned that with the help of mailbox client IP, any FPGA logic can access the Flash once configuration is done. The are of the flash can be divided to store configuration bitstream and the application f/w.

So as of now it resolved all queries. For queries related to integration of debug trace logic, I will open a separate case. We can close this case.

Regards

Sneha

[JingyangTeh_Altera]

Hi

Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 10 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.

Regards

Jingyang, Teh