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Questa not showing signals from verilog models

BrianM
New Contributor I
925 Views

Hello.

 

I've just started using intel Questasim vs intel modelsim and it is faster! Which is great! Time to regress on my laptop went from around 37 minutes to around 25 minutes.

 

However, my regressions had a single test failure (actually a single bit failure). So I need to run a simulation with waveforms to see what is going on and fix the testbench (probably).

 

I already have a .do file for simulating this test, but none of the signals it refers to are found when it tries to load.

 

And when I traverse the design tree in questa, none of my verilog modules show any signals at all. Many of the modules are completely free of Objects.

 

Yet the simulation runs and, except for the one issue I need to debug, completely works!

 

I'm running Questa on linux.

 

Any help would be appreciated.

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4 Replies
BrianM
New Contributor I
846 Views

Well, I remembered the alias created by Quartus Pro:

 

alias ld_debug "
 dev_com
 com
 elab_debug
"

However when I enable that, questa barfs:

# Questa Intel FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# ** Error (suppressible): (vlog-12110) All optimizations are disabled because the -novopt option is in effect. This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for Debug or PLI features, please see the User's Manual section on Preserving Object Visibility with vopt. -novopt option is now deprecated and will be removed in future releases.
# Errors: 1, Warnings: 0

So questa has disabled this option: -voptargs=+acc

 

I can suppress it, I just have to figure out how.

 

It seems to me that the Quartus qsys tool needs to be updated to add an option for enabling access to modules on a module by module basis when it creates msim_setup.tcl.

 

If anyone knows a better way to do this, I'm all ears.

BrianM
New Contributor I
818 Views

Questa> suppress 12110
# Error while executing: suppress
# Usage: suppress [-clear <msg_number>[,<msg_number>,...]] [<msg_number>[,<msg_number>,...]] [<code_string>[, <code_string>, ...]

 

Can someone tell me how to do this?

 

BrianM
New Contributor I
734 Views

For anyone who finds this thread in the future. The fix is to enable access in vlog and in vsim and suppress the error message like this:

From msim_setup.tcl:

if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
set USER_DEFINED_VERILOG_COMPILE_OPTIONS "+acc -suppress 12110"
}
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
set USER_DEFINED_ELAB_OPTIONS "+acc -suppress 12110"
}

BlueRanger
Beginner
668 Views

This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for Debug or PLI features, tellpizzahut please see the User's Manual section on Preserving Object Visibility with vopt. -novopt option is now deprecated and will be removed in future releases.

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